Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73323 )
Change subject: soc/amd: introduce and use PSTATE_MSR macro ......................................................................
soc/amd: introduce and use PSTATE_MSR macro
Instead of adding the P-state number to the PSTATE_0_MSR number to get the P-state MSR number for the rdmsr call, provide a macro that directly calculates the MSR number for a given power state. Also drop the unused PSTATE_[1..4]_MSR definitions which also didn't cover all P-state MSRs available in the hardware.
Signed-off-by: Felix Held felix-coreboot@felixheld.de Change-Id: If85acf556efe82c209e1608e56c05f7a2a748403 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73323 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Elyes Haouas ehaouas@noos.fr Reviewed-by: Fred Reitberger reitbergerfred@gmail.com Reviewed-by: Arthur Heymans arthur@aheymans.xyz --- M src/include/cpu/amd/msr.h M src/soc/amd/cezanne/acpi.c M src/soc/amd/common/block/cpu/tsc/tsc_freq.c M src/soc/amd/glinda/acpi.c M src/soc/amd/mendocino/acpi.c M src/soc/amd/phoenix/acpi.c M src/soc/amd/picasso/acpi.c M src/soc/amd/stoneyridge/tsc_freq.c 8 files changed, 29 insertions(+), 11 deletions(-)
Approvals: build bot (Jenkins): Verified Elyes Haouas: Looks good to me, but someone else must approve Arthur Heymans: Looks good to me, approved Fred Reitberger: Looks good to me, approved
diff --git a/src/include/cpu/amd/msr.h b/src/include/cpu/amd/msr.h index 76e6a8d..1fd7ec7 100644 --- a/src/include/cpu/amd/msr.h +++ b/src/include/cpu/amd/msr.h @@ -40,10 +40,7 @@ /* P-state Status Register */ #define PS_STS_REG 0xC0010063 #define PSTATE_0_MSR 0xC0010064 -#define PSTATE_1_MSR 0xC0010065 -#define PSTATE_2_MSR 0xC0010066 -#define PSTATE_3_MSR 0xC0010067 -#define PSTATE_4_MSR 0xC0010068 +#define PSTATE_MSR(pstate) (PSTATE_0_MSR + (pstate)) #define MSR_PATCH_LOADER 0xC0010020
#define MSR_COFVID_STS 0xC0010071 diff --git a/src/soc/amd/cezanne/acpi.c b/src/soc/amd/cezanne/acpi.c index 631f388..46eaadc 100644 --- a/src/soc/amd/cezanne/acpi.c +++ b/src/soc/amd/cezanne/acpi.c @@ -200,7 +200,7 @@ max_pstate = (rdmsr(PS_LIM_REG).lo & PS_LIM_MAX_VAL_MASK) >> PS_MAX_VAL_SHFT;
for (pstate = 0; pstate <= max_pstate; pstate++) { - pstate_def = rdmsr(PSTATE_0_MSR + pstate); + pstate_def = rdmsr(PSTATE_MSR(pstate));
pstate_enable = (pstate_def.hi & PSTATE_DEF_HI_ENABLE_MASK) >> PSTATE_DEF_HI_ENABLE_SHIFT; diff --git a/src/soc/amd/common/block/cpu/tsc/tsc_freq.c b/src/soc/amd/common/block/cpu/tsc/tsc_freq.c index 55c8665..fbbf399 100644 --- a/src/soc/amd/common/block/cpu/tsc/tsc_freq.c +++ b/src/soc/amd/common/block/cpu/tsc/tsc_freq.c @@ -22,7 +22,7 @@ return mhz;
high_state = rdmsr(PS_LIM_REG).lo & 0x7; - msr = rdmsr(PSTATE_0_MSR + high_state); + msr = rdmsr(PSTATE_MSR(high_state)); if (!(msr.hi & 0x80000000)) die("Unknown error: cannot determine P-state 0\n");
diff --git a/src/soc/amd/glinda/acpi.c b/src/soc/amd/glinda/acpi.c index 31723b1..675ab20 100644 --- a/src/soc/amd/glinda/acpi.c +++ b/src/soc/amd/glinda/acpi.c @@ -203,7 +203,7 @@ max_pstate = (rdmsr(PS_LIM_REG).lo & PS_LIM_MAX_VAL_MASK) >> PS_MAX_VAL_SHFT;
for (pstate = 0; pstate <= max_pstate; pstate++) { - pstate_def = rdmsr(PSTATE_0_MSR + pstate); + pstate_def = rdmsr(PSTATE_MSR(pstate));
pstate_enable = (pstate_def.hi & PSTATE_DEF_HI_ENABLE_MASK) >> PSTATE_DEF_HI_ENABLE_SHIFT; diff --git a/src/soc/amd/mendocino/acpi.c b/src/soc/amd/mendocino/acpi.c index 044b345..fb4d103 100644 --- a/src/soc/amd/mendocino/acpi.c +++ b/src/soc/amd/mendocino/acpi.c @@ -202,7 +202,7 @@ max_pstate = (rdmsr(PS_LIM_REG).lo & PS_LIM_MAX_VAL_MASK) >> PS_MAX_VAL_SHFT;
for (pstate = 0; pstate <= max_pstate; pstate++) { - pstate_def = rdmsr(PSTATE_0_MSR + pstate); + pstate_def = rdmsr(PSTATE_MSR(pstate));
pstate_enable = (pstate_def.hi & PSTATE_DEF_HI_ENABLE_MASK) >> PSTATE_DEF_HI_ENABLE_SHIFT; diff --git a/src/soc/amd/phoenix/acpi.c b/src/soc/amd/phoenix/acpi.c index 09c4a15..25ebc66 100644 --- a/src/soc/amd/phoenix/acpi.c +++ b/src/soc/amd/phoenix/acpi.c @@ -203,7 +203,7 @@ max_pstate = (rdmsr(PS_LIM_REG).lo & PS_LIM_MAX_VAL_MASK) >> PS_MAX_VAL_SHFT;
for (pstate = 0; pstate <= max_pstate; pstate++) { - pstate_def = rdmsr(PSTATE_0_MSR + pstate); + pstate_def = rdmsr(PSTATE_MSR(pstate));
pstate_enable = (pstate_def.hi & PSTATE_DEF_HI_ENABLE_MASK) >> PSTATE_DEF_HI_ENABLE_SHIFT; diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index f6fb9f2..138e743 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -202,7 +202,7 @@ max_pstate = (rdmsr(PS_LIM_REG).lo & PS_LIM_MAX_VAL_MASK) >> PS_MAX_VAL_SHFT;
for (pstate = 0; pstate <= max_pstate; pstate++) { - pstate_def = rdmsr(PSTATE_0_MSR + pstate); + pstate_def = rdmsr(PSTATE_MSR(pstate));
pstate_enable = (pstate_def.hi & PSTATE_DEF_HI_ENABLE_MASK) >> PSTATE_DEF_HI_ENABLE_SHIFT; diff --git a/src/soc/amd/stoneyridge/tsc_freq.c b/src/soc/amd/stoneyridge/tsc_freq.c index 01f2321..0be93aa 100644 --- a/src/soc/amd/stoneyridge/tsc_freq.c +++ b/src/soc/amd/stoneyridge/tsc_freq.c @@ -23,7 +23,7 @@ boost_states = (pci_read_config32(SOC_PM_DEV, CORE_PERF_BOOST_CTRL) >> 2) & 0x7;
- msr = rdmsr(PSTATE_0_MSR + boost_states); + msr = rdmsr(PSTATE_MSR(boost_states)); if (!(msr.hi & 0x80000000)) die("Unknown error: cannot determine P-state 0\n");