[coreboot-gerrit] Change in coreboot[master]: soc/intel: Add Skylake-SP and Cascade Lake support

[Maxim Polyakov (Code Review)]

Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35126 )

Change subject: soc/intel: Add Skylake-SP and Cascade Lake support
......................................................................

Patch Set 7:

(2 comments)

https://review.coreboot.org/c/coreboot/+/35126/6//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/35126/6//COMMIT_MSG@10 
PS6, Line 10: PCI Id
> Add . at the end of sentence.

Done

https://review.coreboot.org/c/coreboot/+/35126/7//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/35126/7//COMMIT_MSG@7 
PS7, Line 7: Add Skylake-SP
> But how you tested? So far there's no coreboot platform published to support skylake-sp server yet.

Not tested yet. We are waiting for Intel to answer the question about fsp for these processors