Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40968 )
Change subject: soc/intel/tigerlake: Clear TBT PCIe root ports BME at exit boot service
......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/40968/4//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/40968/4//COMMIT_MSG@10
PS4, Line 10: enable(BME)
Please add a space before (.
https://review.coreboot.org/c/coreboot/+/40968/4//COMMIT_MSG@11
PS4, Line 11: and devices at exit boot service. In this state with BME bit cleared,
Can you please give a reference, where this is specified?
--
To view, visit
https://review.coreboot.org/c/coreboot/+/40968
To unsubscribe, or for help writing mail filters, visit
https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I9650b9dd4df1f9bee53ae3737b7bf60b2ef8017b
Gerrit-Change-Number: 40968
Gerrit-PatchSet: 4
Gerrit-Owner: John Zhao
john.zhao@intel.com
Gerrit-Reviewer: Alex Levin
levinale@google.com
Gerrit-Reviewer: Caveh Jalali
caveh@chromium.org
Gerrit-Reviewer: Divya S Sasidharan
divya.s.sasidharan@intel.com
Gerrit-Reviewer: Duncan Laurie
dlaurie@chromium.org
Gerrit-Reviewer: Patrick Rudolph
siro@das-labor.org
Gerrit-Reviewer: Prashant Malani
pmalani@google.com
Gerrit-Reviewer: Shamile Khan
shamile.khan@intel.com
Gerrit-Reviewer: Wonkyu Kim
wonkyu.kim@intel.com
Gerrit-Reviewer: build bot (Jenkins)
no-reply@coreboot.org
Gerrit-CC: Paul Menzel
paulepanter@users.sourceforge.net
Gerrit-Comment-Date: Mon, 04 May 2020 13:22:35 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Gerrit-MessageType: comment