Uwe Poeche has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63546 )
Change subject: intel/common/block: provide config switches from APL specific ......................................................................
intel/common/block: provide config switches from APL specific
There are two APL specific config switches for RAPL and min. cpu clock (APL_SKIP_SET_POWER_LIMITS, APL_SKIP_SET_POWER_LIMITS). This switches could be used in future in other CPU platforms. Therefore they moved here with other name to common/block.
Test: mainboards mc_apl1/4/5: compare cpu clock via MSR 0x198 and RAPL settings via MSR 0x610 before and after the change.
Change-Id: I3d63d1b9b6c96586a3c20bf8c1d8001b1d7c4bed Signed-off-by: Uwe Poeche uwe.poeche@siemens.com --- M src/mainboard/siemens/mc_apl1/variants/mc_apl1/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/cpu.c M src/soc/intel/common/block/cpu/Kconfig 9 files changed, 27 insertions(+), 27 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/63546/1
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/Kconfig index ae76f7b..052a58e 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/Kconfig @@ -8,7 +8,7 @@ select RX6110SA_DISABLE_ACPI select DRIVER_SIEMENS_NC_FPGA select NC_FPGA_NOTIFY_CB_READY - select APL_SKIP_SET_POWER_LIMITS + select SOC_INTEL_DISABLE_POWER_LIMITS select DRIVERS_I2C_PTN3460
endif # BOARD_SIEMENS_MC_APL1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig index d690157..306438d 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig @@ -8,6 +8,6 @@ select RX6110SA_DISABLE_ACPI select DRIVER_SIEMENS_NC_FPGA select NC_FPGA_NOTIFY_CB_READY - select APL_SKIP_SET_POWER_LIMITS + select SOC_INTEL_DISABLE_POWER_LIMITS
endif # BOARD_SIEMENS_MC_APL3 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig index 53729c2..a1959a5 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig @@ -4,7 +4,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select DRIVER_INTEL_I210 - select APL_SET_MIN_CLOCK_RATIO + select SOC_INTEL_SET_MIN_CLOCK_RATIO select MAINBOARD_HAS_TPM2 select MAINBOARD_HAS_LPC_TPM select TPM_ON_FAST_SPI diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig index 00d65ce..c3cc43a 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig @@ -8,7 +8,7 @@ select RX6110SA_DISABLE_ACPI select DRIVER_SIEMENS_NC_FPGA select NC_FPGA_NOTIFY_CB_READY - select APL_SKIP_SET_POWER_LIMITS + select SOC_INTEL_DISABLE_POWER_LIMITS select MAINBOARD_HAS_TPM2 select MAINBOARD_HAS_LPC_TPM select TPM_ON_FAST_SPI diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig index af8d058..e6e8e1c 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig @@ -8,7 +8,7 @@ select RX6110SA_DISABLE_ACPI select DRIVER_SIEMENS_NC_FPGA select NC_FPGA_NOTIFY_CB_READY - select APL_SKIP_SET_POWER_LIMITS + select SOC_INTEL_DISABLE_POWER_LIMITS select MAINBOARD_HAS_TPM2 select MAINBOARD_HAS_LPC_TPM select TPM_ON_FAST_SPI diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 08ddfa4..98a4d59 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -348,25 +348,6 @@ default 0xddffc000 depends on INTEL_LPSS_UART_FOR_CONSOLE
-config APL_SKIP_SET_POWER_LIMITS - bool - default n - help - Some Apollo Lake mainboards do not need the Running Average Power - Limits (RAPL) algorithm for a constant power management. - Set this config option to skip the RAPL configuration. - -config APL_SET_MIN_CLOCK_RATIO - bool - depends on !APL_SKIP_SET_POWER_LIMITS - default n - help - If the power budget of the mainboard is limited, it can be useful to - limit the CPU power dissipation at the cost of performance by setting - the lowest possible CPU clock. Enable this option if you need smallest - possible CPU clock. This setting can be overruled by the OS if it has an - p-state driver which can adjust the clock to its need. - # M and N divisor values for clock frequency configuration. # These values get us a 1.836 MHz clock (ideally we want 1.843 MHz) config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 3ee4920..021583f 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -320,7 +320,7 @@ */ p2sb_unhide();
- if (CONFIG(APL_SKIP_SET_POWER_LIMITS)) { + if (CONFIG(SOC_INTEL_DISABLE_POWER_LIMITS)) { printk(BIOS_INFO, "Skip setting RAPL per configuration\n"); } else { config = config_of_soc(); diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index e892017..79a69f5 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -79,11 +79,11 @@ enable_pm_timer_emulation();
/* Set Max Non-Turbo ratio if RAPL is disabled. */ - if (CONFIG(APL_SKIP_SET_POWER_LIMITS)) { + if (CONFIG(SOC_INTEL_DISABLE_POWER_LIMITS)) { cpu_set_p_state_to_max_non_turbo_ratio(); /* Disable speed step */ cpu_set_eist(false); - } else if (CONFIG(APL_SET_MIN_CLOCK_RATIO)) { + } else if (CONFIG(SOC_INTEL_SET_MIN_CLOCK_RATIO)) { cpu_set_p_state_to_min_clock_ratio(); /* Disable speed step */ cpu_set_eist(false); diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig index 378b6a2..961ea95 100644 --- a/src/soc/intel/common/block/cpu/Kconfig +++ b/src/soc/intel/common/block/cpu/Kconfig @@ -136,3 +136,22 @@ help Select this on platforms that do not support Bootguard related MSRs 0x139, MSR_BC_PBEC and 0x13A, MSR_BOOT_GUARD_SACM_INFO. + +config SOC_INTEL_DISABLE_POWER_LIMITS + bool + default n + help + Some Apollo Lake mainboards do not need the Running Average Power + Limits (RAPL) algorithm for a constant power management. + Set this config option to skip the RAPL configuration. + +config SOC_INTEL_SET_MIN_CLOCK_RATIO + bool + depends on !SOC_INTEL_DISABLE_POWER_LIMITS + default n + help + If the power budget of the mainboard is limited, it can be useful to + limit the CPU power dissipation at the cost of performance by setting + the lowest possible CPU clock. Enable this option if you need smallest + possible CPU clock. This setting can be overruled by the OS if it has an + p-state driver which can adjust the clock to its need.