Leroy P Leahy (leroy.p.leahy@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15006
-gerrit
commit afee7f429c2dce8d6958a9c0b87036a391174f38 Author: Lee Leahy leroy.p.leahy@intel.com Date: Mon May 30 14:16:10 2016 -0700
soc/intel/quark: Set temporary I2C base address
Set a temporary I2C base address during romstage.
TEST=Build and run on Galileo Gen2
Change-Id: I4b427c66a4e7e6d30cc611d4d3c40bb0ea36066d Signed-off-by: Lee Leahy leroy.p.leahy@intel.com --- src/soc/intel/quark/include/soc/iomap.h | 3 ++- src/soc/intel/quark/romstage/romstage.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/soc/intel/quark/include/soc/iomap.h b/src/soc/intel/quark/include/soc/iomap.h index 61773d5..1224bcc 100644 --- a/src/soc/intel/quark/include/soc/iomap.h +++ b/src/soc/intel/quark/include/soc/iomap.h @@ -25,7 +25,8 @@ #define UART_BASE_ADDRESS CONFIG_TTYS0_BASE
/* I2C/GPIO Controller */ -#define I2C_GPIO_BASE_ADDRESS 0xa0020000 +#define I2C_BASE_ADDRESS 0xa0020000 +#define GPIO_BASE_ADDRESS 0xa0021000
/* * I/O port address space diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c index c4f9844..c86c2ea 100644 --- a/src/soc/intel/quark/romstage/romstage.c +++ b/src/soc/intel/quark/romstage/romstage.c @@ -52,7 +52,8 @@ static const struct reg_script legacy_gpio_init[] = {
static const struct reg_script i2c_gpio_controller_init[] = { /* Temporarily enable the GPIO controller */ - REG_PCI_WRITE32(PCI_BASE_ADDRESS_1, I2C_GPIO_BASE_ADDRESS), + REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, I2C_BASE_ADDRESS), + REG_PCI_WRITE32(PCI_BASE_ADDRESS_1, GPIO_BASE_ADDRESS), REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_MEMORY), REG_SCRIPT_END };