Attention is currently required from: Damien Zammit, Angel Pons, Patrick Rudolph. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52932 )
Change subject: nb/intel/*: Use acpi_is_wake_s3 ......................................................................
nb/intel/*: Use acpi_is_wake_s3
Change-Id: If71286bde340933e9e102daecb56ae34908fd5f5 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/northbridge/intel/gm45/romstage.c M src/northbridge/intel/haswell/romstage.c M src/northbridge/intel/i945/romstage.c M src/northbridge/intel/ironlake/romstage.c M src/northbridge/intel/pineview/romstage.c M src/northbridge/intel/sandybridge/romstage.c M src/northbridge/intel/x4x/romstage.c M src/southbridge/intel/common/Makefile.inc D src/southbridge/intel/common/pmclib.c D src/southbridge/intel/common/pmclib.h 10 files changed, 7 insertions(+), 64 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/52932/1
diff --git a/src/northbridge/intel/gm45/romstage.c b/src/northbridge/intel/gm45/romstage.c index b87380a..e95c37c 100644 --- a/src/northbridge/intel/gm45/romstage.c +++ b/src/northbridge/intel/gm45/romstage.c @@ -10,7 +10,6 @@ #include <northbridge/intel/gm45/gm45.h> #include <southbridge/intel/i82801ix/i82801ix.h> #include <southbridge/intel/common/gpio.h> -#include <southbridge/intel/common/pmclib.h> #include <southbridge/intel/common/pmutil.h> #include <string.h>
@@ -59,7 +58,7 @@ dmibar_clrbits16(0x204, 3 << 10);
/* Check for S3 resume. */ - s3resume = southbridge_detect_s3_resume(); + s3resume = acpi_is_wakeup_s3();
/* RAM initialization */ enter_raminit_or_reset(); diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index 28a0c79..e8984df 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -10,7 +10,6 @@ #include <security/intel/txt/txt_register.h> #include <northbridge/intel/haswell/haswell.h> #include <northbridge/intel/haswell/raminit.h> -#include <southbridge/intel/common/pmclib.h> #include <southbridge/intel/lynxpoint/pch.h>
void __weak mb_late_romstage_setup(void) @@ -30,7 +29,7 @@ haswell_early_initialization(); printk(BIOS_DEBUG, "Back from haswell_early_initialization()\n");
- const int s3resume = southbridge_detect_s3_resume(); + const int s3resume = acpi_is_wakeup_s3();
elog_boot_notify(s3resume);
diff --git a/src/northbridge/intel/i945/romstage.c b/src/northbridge/intel/i945/romstage.c index efcf0d6..1274bfc 100644 --- a/src/northbridge/intel/i945/romstage.c +++ b/src/northbridge/intel/i945/romstage.c @@ -7,7 +7,6 @@ #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h> -#include <southbridge/intel/common/pmclib.h>
__weak void mainboard_lpc_decode(void) { @@ -44,7 +43,7 @@ i82801gx_early_init(); i945_early_initialization();
- s3resume = southbridge_detect_s3_resume(); + s3resume = acpi_is_wakeup_s3();
mainboard_pre_raminit_config(s3resume);
diff --git a/src/northbridge/intel/ironlake/romstage.c b/src/northbridge/intel/ironlake/romstage.c index 8d3cfd6..cf850d9 100644 --- a/src/northbridge/intel/ironlake/romstage.c +++ b/src/northbridge/intel/ironlake/romstage.c @@ -14,7 +14,6 @@ #include <device/device.h> #include <northbridge/intel/ironlake/chip.h> #include <northbridge/intel/ironlake/raminit.h> -#include <southbridge/intel/common/pmclib.h> #include <southbridge/intel/ibexpeak/pch.h> #include <southbridge/intel/ibexpeak/me.h>
@@ -34,7 +33,7 @@
early_pch_init();
- s3resume = southbridge_detect_s3_resume(); + s3resume = acpi_is_wakeup_s3(); if (s3resume) { u8 reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); if (!(reg8 & 0x20)) { diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c index 5e5420c..0ee7191 100644 --- a/src/northbridge/intel/pineview/romstage.c +++ b/src/northbridge/intel/pineview/romstage.c @@ -7,7 +7,6 @@ #include <cf9_reset.h> #include <romstage_handoff.h> #include <southbridge/intel/i82801gx/i82801gx.h> -#include <southbridge/intel/common/pmclib.h> #include <arch/romstage.h> #include <cpu/x86/lapic.h> #include "raminit.h" @@ -39,7 +38,7 @@
post_code(0x30);
- s3resume = southbridge_detect_s3_resume(); + s3resume = acpi_is_wakeup_s3();
if (s3resume) { boot_path = BOOT_PATH_RESUME; diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index d6e7ee9..9e1cee89 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -11,7 +11,6 @@ #include <device/device.h> #include <northbridge/intel/sandybridge/chip.h> #include <southbridge/intel/bd82x6x/pch.h> -#include <southbridge/intel/common/pmclib.h> #include <elog.h>
__weak void mainboard_early_init(int s3_resume) @@ -50,7 +49,7 @@ systemagent_early_init(); printk(BIOS_DEBUG, "Back from systemagent_early_init()\n");
- s3resume = southbridge_detect_s3_resume(); + s3resume = acpi_is_wakeup_s3();
elog_boot_notify(s3resume);
diff --git a/src/northbridge/intel/x4x/romstage.c b/src/northbridge/intel/x4x/romstage.c index 1695ddd..e6416ed 100644 --- a/src/northbridge/intel/x4x/romstage.c +++ b/src/northbridge/intel/x4x/romstage.c @@ -2,7 +2,6 @@
#include <console/console.h> #include <romstage_handoff.h> -#include <southbridge/intel/common/pmclib.h> #include <arch/romstage.h>
#if CONFIG(SOUTHBRIDGE_INTEL_I82801JX) @@ -32,7 +31,7 @@
x4x_early_init();
- s3_resume = southbridge_detect_s3_resume(); + s3_resume = acpi_is_wakeup_s3(); mb_pre_raminit_setup(s3_resume);
if (s3_resume) diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index c468d5c..56ab596 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -15,9 +15,6 @@ ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus_ops.c
-bootblock-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB) += pmclib.c -romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB) += pmclib.c - ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG) += watchdog.c
all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE) += pmbase.c diff --git a/src/southbridge/intel/common/pmclib.c b/src/southbridge/intel/common/pmclib.c deleted file mode 100644 index 4d207d6..0000000 --- a/src/southbridge/intel/common/pmclib.c +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <stdint.h> -#include <acpi/acpi.h> -#include <console/console.h> - -#include "pmclib.h" -#include "pmbase.h" -#include "pmutil.h" - -int southbridge_detect_s3_resume(void) -{ - u32 pm1_cnt; - u16 pm1_sts; - int is_s3 = 0; - - /* Check PM1_STS[15] to see if we are waking from Sx */ - pm1_sts = read_pmbase16(PM1_STS); - if (pm1_sts & WAK_STS) { - /* Read PM1_CNT[12:10] to determine which Sx state */ - pm1_cnt = read_pmbase32(PM1_CNT); - if (((pm1_cnt >> 10) & 7) == SLP_TYP_S3) - is_s3 = 1; - } - if (is_s3) { - if (!acpi_s3_resume_allowed()) { - printk(BIOS_DEBUG, "SB: Resume from S3 detected, but disabled.\n"); - return 0; - } - - printk(BIOS_DEBUG, "SB: Resume from S3 detected.\n"); - } - - return is_s3; -} diff --git a/src/southbridge/intel/common/pmclib.h b/src/southbridge/intel/common/pmclib.h deleted file mode 100644 index fd87a01..0000000 --- a/src/southbridge/intel/common/pmclib.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef INTEL_COMMON_PMCLIB_H -#define INTEL_COMMON_PMCLIB_H - -/* - * Returns 1 if platform was in ACPI S3 power state and CONFIG(HAVE_ACPI_RESUME) - * is enabled else returns 0. - */ -int southbridge_detect_s3_resume(void); - -#endif