[coreboot-gerrit] Change in coreboot[master]: nb/intel/sandybridge: Clean up TC_OTHP writes

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47490 )

Change subject: nb/intel/sandybridge: Clean up TC_OTHP writes
......................................................................

nb/intel/sandybridge: Clean up TC_OTHP writes

ODT stretch is configured for both slots in `dram_odt_stretch`.

Change-Id: I3a9076afec96e33cfdd12f9b78ca4101b3776dab
Signed-off-by: Angel Pons 
---
M src/northbridge/intel/sandybridge/raminit_common.c
1 file changed, 3 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/47490/1

diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index 20c048f..8a4b25b 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -166,7 +166,7 @@

void dram_timing_regs(ramctr_timing *ctrl)
 {
-	u32 reg, addr, val32;
+	u32 reg, val32;
    int channel;

FOR_ALL_CHANNELS {
@@ -193,14 +193,13 @@
    	MCHBAR32(TC_RAP_ch(channel)) = reg;

/* Other parameters */
-		addr = TC_OTHP_ch(channel);
    	reg = 0;
    	reg |= (ctrl->tXPDLL << 0);
    	reg |= (ctrl->tXP    << 5);
    	reg |= (ctrl->tAONPD << 8);
    	reg |= 0xa0000;
-		printram("OTHP [%x] = %x\n", addr, reg);
-		MCHBAR32(addr) = reg;
+		printram("OTHP [%x] = %x\n", TC_OTHP_ch(channel), reg);
+		MCHBAR32(TC_OTHP_ch(channel)) = reg;

/* Debug parameters - only applies to Ivy Bridge */
    	if (IS_IVY_CPU(ctrl->cpu)) {
@@ -219,8 +218,6 @@
    		MCHBAR32(TC_DTP_ch(channel)) = reg;
    	}

-		MCHBAR32_OR(addr, 0x00020000);
-
    	dram_odt_stretch(ctrl, channel);

/*