Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81466?usp=email )
Change subject: mb/google/cyan: Remove blank lines before '}' and after '{' ......................................................................
mb/google/cyan: Remove blank lines before '}' and after '{'
Change-Id: Ibb02623cf2d2880d9b452f51159509da0596f0ec Signed-off-by: Elyes Haouas ehaouas@noos.fr --- M src/mainboard/google/cyan/variants/banon/romstage.c M src/mainboard/google/cyan/variants/celes/ramstage.c M src/mainboard/google/cyan/variants/edgar/romstage.c M src/mainboard/google/cyan/variants/kefka/ramstage.c M src/mainboard/google/cyan/variants/kefka/romstage.c M src/mainboard/google/cyan/variants/reks/romstage.c M src/mainboard/google/cyan/variants/relm/romstage.c M src/mainboard/google/cyan/variants/setzer/romstage.c M src/mainboard/google/cyan/variants/terra/romstage.c M src/mainboard/google/cyan/variants/ultima/gpio.c 10 files changed, 0 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/81466/1
diff --git a/src/mainboard/google/cyan/variants/banon/romstage.c b/src/mainboard/google/cyan/variants/banon/romstage.c index 7dcf622..a711e19 100644 --- a/src/mainboard/google/cyan/variants/banon/romstage.c +++ b/src/mainboard/google/cyan/variants/banon/romstage.c @@ -13,7 +13,6 @@ * RAMID = 12 - 2GiB Micron MT52L256M32D1PF */ if (ram_id == 4 || ram_id == 12) { - /* * For new micron part, it requires read/receive * enable training before sending cmds to get MR8. diff --git a/src/mainboard/google/cyan/variants/celes/ramstage.c b/src/mainboard/google/cyan/variants/celes/ramstage.c index a126a48..a287838 100644 --- a/src/mainboard/google/cyan/variants/celes/ramstage.c +++ b/src/mainboard/google/cyan/variants/celes/ramstage.c @@ -5,7 +5,6 @@ void board_silicon_USB2_override(SILICON_INIT_UPD *params) { if (SocStepping() >= SocD0) { - //Follow Intel recommendation to set //BSW D-stepping PERPORTRXISET 2 (low strength) params->Usb2Port0PerPortPeTxiSet = 7; diff --git a/src/mainboard/google/cyan/variants/edgar/romstage.c b/src/mainboard/google/cyan/variants/edgar/romstage.c index 7b1d8cc..af55b8a 100644 --- a/src/mainboard/google/cyan/variants/edgar/romstage.c +++ b/src/mainboard/google/cyan/variants/edgar/romstage.c @@ -13,7 +13,6 @@ * RAMID = 7 - 2GiB Micron MT52L256M32D1PF-107 */ if (ram_id == 5 || ram_id == 7) { - /* * For new micron part, it requires read/receive * enable training before sending cmds to get MR8. diff --git a/src/mainboard/google/cyan/variants/kefka/ramstage.c b/src/mainboard/google/cyan/variants/kefka/ramstage.c index e1fd33a..96d53c2 100644 --- a/src/mainboard/google/cyan/variants/kefka/ramstage.c +++ b/src/mainboard/google/cyan/variants/kefka/ramstage.c @@ -5,7 +5,6 @@ void board_silicon_USB2_override(SILICON_INIT_UPD *params) { if (SocStepping() >= SocD0) { - //Follow Intel recommendation to set //BSW D-stepping PERPORTRXISET 2 (low strength) params->D0Usb2Port0PerPortRXISet = 2; diff --git a/src/mainboard/google/cyan/variants/kefka/romstage.c b/src/mainboard/google/cyan/variants/kefka/romstage.c index 9492b84..d5e8883 100644 --- a/src/mainboard/google/cyan/variants/kefka/romstage.c +++ b/src/mainboard/google/cyan/variants/kefka/romstage.c @@ -13,7 +13,6 @@ * RAMID = 3 - 2GiB Micron MT52L256M32D1PF-107 */ if (ram_id == 2 || ram_id == 3) { - /* * For new micron part, it requires read/receive * enable training before sending cmds to get MR8. diff --git a/src/mainboard/google/cyan/variants/reks/romstage.c b/src/mainboard/google/cyan/variants/reks/romstage.c index c8fd30b..4b817e5 100644 --- a/src/mainboard/google/cyan/variants/reks/romstage.c +++ b/src/mainboard/google/cyan/variants/reks/romstage.c @@ -13,7 +13,6 @@ * RAMID = 2 - 2GiB Micron MT52L256M32D1PF-107 */ if (ram_id == 2 || ram_id == 0xA) { - /* * For new micron part, it requires read/receive * enable training before sending cmds to get MR8. diff --git a/src/mainboard/google/cyan/variants/relm/romstage.c b/src/mainboard/google/cyan/variants/relm/romstage.c index c8fd30b..4b817e5 100644 --- a/src/mainboard/google/cyan/variants/relm/romstage.c +++ b/src/mainboard/google/cyan/variants/relm/romstage.c @@ -13,7 +13,6 @@ * RAMID = 2 - 2GiB Micron MT52L256M32D1PF-107 */ if (ram_id == 2 || ram_id == 0xA) { - /* * For new micron part, it requires read/receive * enable training before sending cmds to get MR8. diff --git a/src/mainboard/google/cyan/variants/setzer/romstage.c b/src/mainboard/google/cyan/variants/setzer/romstage.c index e8c3c1c..21e1569 100644 --- a/src/mainboard/google/cyan/variants/setzer/romstage.c +++ b/src/mainboard/google/cyan/variants/setzer/romstage.c @@ -13,7 +13,6 @@ * RAMID = 5 - 2GiB Micron MT52L256M32D1PF-107 */ if (ram_id == 4 || ram_id == 5) { - /* * For new micron part, it requires read/receive * enable training before sending cmds to get MR8. diff --git a/src/mainboard/google/cyan/variants/terra/romstage.c b/src/mainboard/google/cyan/variants/terra/romstage.c index 5bdd7fe..531f1ea 100644 --- a/src/mainboard/google/cyan/variants/terra/romstage.c +++ b/src/mainboard/google/cyan/variants/terra/romstage.c @@ -13,7 +13,6 @@ * RAMID = 11 - 4GiB Micron MT52L256M32D1PF-107 */ if (ram_id == 3 || ram_id == 11) { - /* * For new micron part, it requires read/receive * enable training before sending cmds to get MR8. diff --git a/src/mainboard/google/cyan/variants/ultima/gpio.c b/src/mainboard/google/cyan/variants/ultima/gpio.c index ede6229..13cc639 100644 --- a/src/mainboard/google/cyan/variants/ultima/gpio.c +++ b/src/mainboard/google/cyan/variants/ultima/gpio.c @@ -237,5 +237,4 @@ struct soc_gpio_config *mainboard_get_gpios(void) { return &gpio_config; - }