Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45094 )
Change subject: soc/intel/tigerlake: Select USE_CAR_NEM_ENHANCED_V2 for tigerlake ......................................................................
soc/intel/tigerlake: Select USE_CAR_NEM_ENHANCED_V2 for tigerlake
Selects Cache QoS mask MSR programming flow for Tigerlake SoC.
BUG=b:145958015 TEST= Build and boot to Chrome OS on TGL-UP3 RVP. Recipe used: 1. Patch https://review.coreboot.org/c/coreboot/+/43494 that implements calculation of CQOS mask dynamically based on stack size usage & incorporates Tigerlake SoC specific programming flow. 2. QS Engineering Microcode based on 0x56 Official Microcode with LLC CQOS change. 3. QS SoC Part
Signed-off-by: Shreesh Chhabbi shreesh.chhabbi@intel.corp-partner.google.com Change-Id: I602d93eb4f8243ec49993b00691140d9a6cf5733 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45094 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/soc/intel/tigerlake/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index cdec3ef..826f8af 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -25,7 +25,7 @@ select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE - select INTEL_CAR_NEM #TODO - Enable INTEL_CAR_NEM_ENHANCED + select USE_CAR_NEM_ENHANCED_V2 select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select IOAPIC