[coreboot-gerrit] Change in ...coreboot[master]: soc/amd/stoneyridge: Add ACPI D3Cold support for SD Controller

[Raul Rangel (Code Review)]

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32433

Change subject: soc/amd/stoneyridge: Add ACPI D3Cold support for SD Controller
......................................................................

soc/amd/stoneyridge: Add ACPI D3Cold support for SD Controller

We need to support entering D3Cold from the OS to workaround a bug in
the SDHC where the data lines get stuck always reading zeros.

BUG=b:122749418
TEST=Verified the linux kernel can transition between D3 and D0

Change-Id: Ifbf48f20c03a752ce3ff773296b536e92db16a62
Signed-off-by: Raul E Rangel 
---
M src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl
1 file changed, 34 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/32433/1

diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl
index 15e4d2f..2139f8d 100644
--- a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl
+++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl
@@ -56,6 +56,16 @@
 /* 0:14.7 - SD Controller */
 Device(SDCN) {
    Name(_ADR, 0x00140007)
+
+	Method(_PS0) {
+		FDDC(24, 0)
+	}
+	Method(_PS3) {
+		FDDC(24, 3)
+	}
+	Method(_PSC) {
+		Return(SDTD)
+	}
 } /* end SDCN */

Name(CRES, ResourceTemplate() {
@@ -286,8 +296,9 @@
    offset (0x1e70), /* SD D3 Control */
    SDTD, 2,
    , 1,
+	SDPD, 1,
    , 1,
-	, 2,
+	, 1,
    SDRT, 1,
    SDSC, 1,

@@ -433,7 +444,17 @@
 /* todo			Case(15) { STD0()} */ /* SATA */
    		Case(18) { U2D0()} /* EHCI */
    		Case(23) { U3D0()} /* XHCI */
-/* todo			Case(24) { SDD0()} */ /* SD   */
+			Case(24) {
+				/* Enable Power */
+				Store(One, SDPD)
+				Store(SDDS, Local0)
+				while(LNotEqual(Local0,0x7)) {
+					Store(SDDS, Local0)
+				}
+
+				/* D0-uninitialized */
+				Store(0x00, SDTD)
+			}
    	}
    } else {
    	/* put device into D3cold */
@@ -489,7 +510,17 @@
 /* todo			Case(15) { STD3()} */ /* SATA */
    		Case(18) { U2D3()} /* EHCI */
    		Case(23) { U3D3()} /* XHCI */
-/* todo			Case(24) { SDD3()} */ /* SD   */
+			Case(24) {
+				/* Disable power */
+				Store(Zero, SDPD)
+				Store(SDDS, Local0)
+				while(LNotEqual(Local0,0x0)) {
+					Store(SDDS, Local0)
+				}
+
+				/* D3 */
+				Store(0x03, SDTD)
+			}
    	}
    	/* Turn off Power */
    	if(LEqual(I0TD, 3)) {