Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Paul Menzel, Tim Wawrzynczak, Patrick Rudolph. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55254 )
Change subject: soc/intel/alderlake: Update PMC Descriptor for Alder lake B0 silicon ......................................................................
Patch Set 6:
(6 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/55254/comment/4c1f0a24_e06dbb96 PS5, Line 7: Alderlake
Alder Lake
Ack
https://review.coreboot.org/c/coreboot/+/55254/comment/9c818f34_629721c8 PS5, Line 13: not updated.
Please add the output of the new messages.
Ack
File src/soc/intel/alderlake/romstage/romstage.c:
https://review.coreboot.org/c/coreboot/+/55254/comment/dab7eb88_7adc8638 PS5, Line 38: #define GLOBAL_RESET_IS_NOT_REQUIRED 2
Align numbers with tabs as above?
Ack
https://review.coreboot.org/c/coreboot/+/55254/comment/bcc216a0_1b50cadb PS5, Line 132: int8_t
Why? Please use generic types if not otherwise necessary. Also below.
Ack
https://review.coreboot.org/c/coreboot/+/55254/comment/a36035a1_37ab4d12 PS5, Line 142: uint8_t
Ditto.
Ack
https://review.coreboot.org/c/coreboot/+/55254/comment/dec5d162_7a12715c PS5, Line 155: if (si_desc_buf[PMC_DESC_7_BYTE3] == 0x44) {
One space before ==.
Ack