[coreboot-gerrit] Change in ...coreboot[master]: mediatek/mt8183: fix mode register setting fail issue

[huayang duan (Code Review)]

huayang duan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32284 )

Change subject: mediatek/mt8183: fix mode register setting fail issue
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Patch Set 3:

(1 comment)

https://review.coreboot.org/#/c/32284/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/#/c/32284/1//COMMIT_MSG@9 
PS1, Line 9: the mode register setting of DRAM maybe failed without delay operate,
           : need add delay after each MR write.
> How can I access the code, you released to Google?

void DramcModeRegWrite(DRAMC_CTX_T *p, U8 u1MRIdx, U8 u1Value)
{
    U32 counter=0;
    U32 u4Rank = 0;
    U32 u4register_024;

u4register_024 = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL));
        CKEFixOnOff(p, CKE_FIXON, CKE_WRITE_TO_ONE_CHANNEL);
    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MRS), u1MRIdx, MRS_MRSMA);
    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MRS), u1Value, MRS_MRSOP);

// MRW command will be fired when MRWEN 0->1
    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMD), 1, SPCMD_MRWEN);

// wait MRW command fired.
    u4Rank = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MRS), MRS_MRSRK);
    while(u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP), SPCMDRESP_MRW_RESPONSE) ==0)
    {
        counter++;
        mcSHOW_DBG_MSG2(("wait MRW command Rank%d MR%d =0x%x fired (%d)\n", u4Rank, u1MRIdx, u1Value, counter));
        mcDELAY_US(1);
    }

// Set MRWEN =0 for next time MRW.
    vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMD), 0, SPCMD_MRWEN);
    vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL), u4register_024); //restore CKEFIXON value 
}