Anil Kumar K has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55240 )
Change subject: vc/intel/fsp/fsp2_0/alderlake: Update MemInfoHob.h as per changes in FSP v2127_00 onwards ......................................................................
vc/intel/fsp/fsp2_0/alderlake: Update MemInfoHob.h as per changes in FSP v2127_00 onwards
With XMP3.0 support added for DDR5 in ADL, the MEMORY_INFO_DATA_HOB structure changed and these changes need to be aligned in vendorcode. To align the structres we update the MemInfoHob header file in vendorcode
Bug=None Branch=None Test=build coreboot and boot on ADLRVP . Confirm the mosys command displays memory info correctly $mosys memory spd print all
Signed-off-by: Anil Kumar anil.kumar.k@intel.com Change-Id: I86bc11c845d836f39ef5c3d748c5fbb1d098cac0 --- M src/vendorcode/intel/fsp/fsp2_0/alderlake/MemInfoHob.h 1 file changed, 31 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/55240/1
diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/MemInfoHob.h index 31047af..4898bc8 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake/MemInfoHob.h +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/MemInfoHob.h @@ -27,6 +27,9 @@ #define MAX_NODE 2 #define MAX_CH 4 #define MAX_DIMM 2 +// Must match definitions in +// Intel\ClientOneSiliconPkg\IpBlock\MemoryInit\Mtl\Include\MrcInterface.h +#define HOB_MAX_SAGV_POINTS 4
/// /// Host reset states from MRC. @@ -129,23 +132,17 @@ // // Matches MrcDdrType enum in MRC // -#ifndef MRC_DDR_TYPE_DDR4 -#define MRC_DDR_TYPE_DDR4 0 +#ifndef MRC_DDR_TYPE_DDR5 +#define MRC_DDR_TYPE_DDR5 1 #endif -#ifndef MRC_DDR_TYPE_DDR3 -#define MRC_DDR_TYPE_DDR3 1 -#endif -#ifndef MRC_DDR_TYPE_LPDDR3 -#define MRC_DDR_TYPE_LPDDR3 2 +#ifndef MRC_DDR_TYPE_LPDDR5 +#define MRC_DDR_TYPE_LPDDR5 2 #endif #ifndef MRC_DDR_TYPE_LPDDR4 #define MRC_DDR_TYPE_LPDDR4 3 #endif -#ifndef MRC_DDR_TYPE_WIO2 -#define MRC_DDR_TYPE_WIO2 4 -#endif #ifndef MRC_DDR_TYPE_UNKNOWN -#define MRC_DDR_TYPE_UNKNOWN 5 +#define MRC_DDR_TYPE_UNKNOWN 4 #endif
#define MAX_PROFILE_NUM 4 // number of memory profiles supported @@ -182,6 +179,10 @@ UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group. } MRC_CH_TIMING;
+typedef struct { + UINT16 tRDPRE; ///< Read CAS to Precharge cmd delay +} MRC_IP_TIMING; + /// /// Memory SMBIOS & OC Memory Data Hob /// @@ -224,6 +225,20 @@ UINT8 Rsvd[2]; } PSMI_MEM_INFO;
+/// This data structure contains per-SaGv timing values that are considered output by the MRC. +typedef struct { + UINT32 DataRate; ///< The memory rate for the current SaGv Point in units of MT/s + MRC_CH_TIMING JedecTiming; ///< Timings used for this entry's corresponding SaGv Point - derived from JEDEC SPD spec + MRC_IP_TIMING IpTiming; ///< Timings used for this entry's corresponding SaGv Point - IP specific +} HOB_SAGV_TIMING_OUT; + +/// This data structure contains SAGV config values that are considered output by the MRC. +typedef struct { + UINT32 NumSaGvPointsEnabled; ///< Count of the total number of SAGV Points enabled. + UINT32 SaGvPointMask; ///< Bit mask where each bit indicates an enabled SAGV point. + HOB_SAGV_TIMING_OUT SaGvTiming[HOB_MAX_SAGV_POINTS]; +} HOB_SAGV_INFO; + typedef struct { UINT8 Revision; UINT16 DataWidth; ///< Data width, in bits, of this memory device @@ -244,11 +259,16 @@ UINT32 TotalPhysicalMemorySize; UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist. UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs. + UINT8 XmpConfigWarning; ///< If XMP capable DIMMs config support only 1DPC, but 2DPC is installed UINT8 Ratio; ///< DDR Frequency Ratio, Max Value 255 UINT8 RefClk; UINT32 VddVoltage[MAX_PROFILE_NUM]; + UINT32 VddqVoltage[MAX_PROFILE_NUM]; + UINT32 VppVoltage[MAX_PROFILE_NUM]; CONTROLLER_INFO Controller[MAX_NODE]; UINT16 Ratio_UINT16; ///< DDR Frequency Ratio, used for programs that require ratios higher then 255 + UINT32 NumPopulatedChannels; ///< Total number of memory channels populated + HOB_SAGV_INFO SagvConfigInfo; ///< This data structure contains SAGV config values that are considered output by the MRC. } MEMORY_INFO_DATA_HOB;
/**