[coreboot-gerrit] [XS] Change in coreboot[main]: src/soc/amd/glinda: Update the PCIE MMCONFIG base address and size fo...

[Anand Vaikar (Code Review)]

Anand Vaikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79832?usp=email )

Change subject: src/soc/amd/glinda: Update the PCIE MMCONFIG base address and size for glinda
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src/soc/amd/glinda: Update the PCIE MMCONFIG base address and size for glinda

The PCIE MMCONFIG base address value and size is updated correctly to
access the PCIE config space registers.

TEST=Verified that PCIE enumeration takes place in boot log
and config space registers are accessible.

Change-Id: Ifa8377df7a2973a88d414c217b5ed114c8ae5cc3
Signed-off-by: Anand Vaikar 
---
M src/soc/amd/glinda/Kconfig
1 file changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/79832/1

diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig
index a3b0ea6..dd362e0 100644
--- a/src/soc/amd/glinda/Kconfig
+++ b/src/soc/amd/glinda/Kconfig
@@ -233,10 +233,10 @@
    default "apu/amdfw"

config ECAM_MMCONF_BASE_ADDRESS
-	default 0xF8000000
+	default 0xE0000000

config ECAM_MMCONF_BUS_NUMBER
-	default 64
+	default 256

config MAX_CPUS
    int