Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36914 )
Change subject: binaryPI: implement C bootblock ......................................................................
Patch Set 13:
(4 comments)
https://review.coreboot.org/c/coreboot/+/36914/8/src/drivers/amd/agesa/cache... File src/drivers/amd/agesa/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/36914/8/src/drivers/amd/agesa/cache... PS8, Line 142: OSFXSR [
I remember I had problems when I placed it later, will test more and maybe remove it if it ends up r […]
I just noticed neither SSE nor SSE2 is selected for any AMD AGESA or binaryPI... Although it is supported. Probably these lines will not be required if I select it in Kconfig
https://review.coreboot.org/c/coreboot/+/36914/8/src/drivers/amd/agesa/cache... PS8, Line 150: x1b
LAPIC_BASE_MSR
Done
https://review.coreboot.org/c/coreboot/+/36914/8/src/drivers/amd/agesa/cache... PS8, Line 152: 256
LAPIC_BASE_MSR_BOOTSTRAP_PROCESSOR
Done
https://review.coreboot.org/c/coreboot/+/36914/8/src/drivers/amd/agesa/cache... PS8, Line 159: %esp
It can be found in src/vendorcode/amd/pi/<family>/binaryPI/gcccar.inc for each family: […]
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