Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45849 )
Change subject: soc/intel/xeon_sp/cpx: Make devicetree config and ops generic ......................................................................
soc/intel/xeon_sp/cpx: Make devicetree config and ops generic
Prepare for common ACPI and de-duplication. Change the mainboard devicetree so that: soc_intel_xeon_sp_cpx_ops -> soc_intel_xeon_sp_ops soc_intel_xeon_sp_cpx_config -> soc_intel_xeon_sp_config
This allows for common code between cpx and skx in future changes.
Change-Id: Iecbe94a0dd395688d0c15e3f67f703e5ac4caa23 Signed-off-by: Marc Jones marcjones@sysproconsulting.com --- M src/mainboard/intel/cedarisland_crb/devicetree.cb M src/mainboard/ocp/deltalake/devicetree.cb M src/soc/intel/xeon_sp/cpx/chip.c M src/soc/intel/xeon_sp/cpx/chip.h M src/soc/intel/xeon_sp/cpx/soc_acpi.c 5 files changed, 6 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/45849/1
diff --git a/src/mainboard/intel/cedarisland_crb/devicetree.cb b/src/mainboard/intel/cedarisland_crb/devicetree.cb index a82f022..9bca7b4 100644 --- a/src/mainboard/intel/cedarisland_crb/devicetree.cb +++ b/src/mainboard/intel/cedarisland_crb/devicetree.cb @@ -1,4 +1,4 @@ -chip soc/intel/xeon_sp/cpx +chip soc/intel/xeon_sp device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/ocp/deltalake/devicetree.cb b/src/mainboard/ocp/deltalake/devicetree.cb index d51391d..0883244 100644 --- a/src/mainboard/ocp/deltalake/devicetree.cb +++ b/src/mainboard/ocp/deltalake/devicetree.cb @@ -1,6 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-or-later
-chip soc/intel/xeon_sp/cpx +chip soc/intel/xeon_sp
register "pirqa_routing" = "PCH_IRQ11" register "pirqb_routing" = "PCH_IRQ10" diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index 5ee7f6c..41bed62 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -609,7 +609,7 @@ p2sb_unhide(); }
-struct chip_operations soc_intel_xeon_sp_cpx_ops = { +struct chip_operations soc_intel_xeon_sp_ops = { CHIP_NAME("Intel Cooperlake-SP") .enable_dev = chip_enable_dev, .init = chip_init, diff --git a/src/soc/intel/xeon_sp/cpx/chip.h b/src/soc/intel/xeon_sp/cpx/chip.h index e7c146c..3dcc406 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.h +++ b/src/soc/intel/xeon_sp/cpx/chip.h @@ -29,7 +29,7 @@ PcieGen3 } pcie_link_speed;
-struct soc_intel_xeon_sp_cpx_config { +struct soc_intel_xeon_sp_config { /* Common struct containing soc config data required by common code */ struct soc_intel_common_config common_soc_config;
@@ -97,7 +97,7 @@ uint32_t tcc_offset; };
-typedef struct soc_intel_xeon_sp_cpx_config config_t; +typedef struct soc_intel_xeon_sp_config config_t;
/* soc acpi function prototypes. To be removed when acpi.c is replaced by common/acpi.c */ void cpx_generate_p_state_entries(int core, int cores_per_package); diff --git a/src/soc/intel/xeon_sp/cpx/soc_acpi.c b/src/soc/intel/xeon_sp/cpx/soc_acpi.c index 1aa1192..63f82ae 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/cpx/soc_acpi.c @@ -690,7 +690,7 @@ acpi_slit_t *slit; acpi_dmar_t *dmar;
- const struct soc_intel_xeon_sp_cpx_config *const config = config_of(device); + const struct soc_intel_xeon_sp_config *const config = config_of(device);
/* SRAT */ current = ALIGN(current, 8);