[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/{skylake,cannonlake,icelake}: Correct GPIO IRQ start map

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31245 )

Change subject: soc/intel/{skylake,cannonlake,icelake}: Correct GPIO IRQ start map
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Patch Set 1:

(1 comment)

https://review.coreboot.org/#/c/31245/1/src/soc/intel/cannonlake/include/soc... 
File src/soc/intel/cannonlake/include/soc/itss.h:

https://review.coreboot.org/#/c/31245/1/src/soc/intel/cannonlake/include/soc... 
PS1, Line 19: 24
the purpose of making it 50 is that to ensure we are taking snap shot between IPC1-IPCn and excluding IPC0 register entry.