Attention is currently required from: Arthur Heymans, Patrick Georgi, Maulik V Vaghela, Rizwan Qureshi, Sridhar Siricilla, Werner Zeh, Angel Pons, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62566 )
Change subject: intel/block/cpu: Keep flash region cached until the payload is loaded ......................................................................
Patch Set 2:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62566/comment/e8e397e9_270ad2f5 PS2, Line 10: done by FSP @Werner, few clarification questions:
1. There are few options (unfortunately in coreboot to perform the MP init by different agents, as: coreboot native MP Init, FSP-S does the MP Init and finally the hybrid approach where coreboot does the MP Init and FSP runs the feature programming using MP PPI). Now when you are saying MP Init done by FSP, which one do you mean?
2. I kind of sense, you are taking about hybrid approach using MP PPI (USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI) and not the USE_INTEL_FSP_MP_INIT Kconfig.
https://review.coreboot.org/c/coreboot/+/62566/comment/5ff796d5_dbbf9b3c PS2, Line 12: done by FSP Is this like FSP doing MP Init USE_INTEL_FSP_MP_INIT?
https://review.coreboot.org/c/coreboot/+/62566/comment/9ac58d14_b9aa7241 PS2, Line 19: uncached flash : range I thought flashed mapped range is always cached and DRAM resource allocation is not clearing that. (I don't have latest coreboot log with DISPLAY_MTRRS enable to verify this observation)
File src/soc/intel/common/block/cpu/mp_init.c:
https://review.coreboot.org/c/coreboot/+/62566/comment/846610e8_8e7e6bc1 PS2, Line 164: MP_SERVICES_PPI Adding Intel ADL team to check if they are also seeing this regression. MP_SERVICES_PPI is selected on ADL.