[coreboot-gerrit] Change in coreboot[master]: coreboot_tables: Add PCIe info to coreboot table

[Julius Werner (Code Review)]

Attention is currently required from: Shelley Chen, Hung-Te Lin, Nico Huber, Paul Menzel, Rex-BC Chen, Arthur Heymans, Yu-Ping Wu, Jianjun Wang.
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63251 )

Change subject: coreboot_tables: Add PCIe info to coreboot table
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Patch Set 19:

(1 comment)

Patchset:

PS9:
> I'm fine with that.

coreboot table entry formats should generally not be changed after they have been introduced (although in this case if Google is the only one using this it would probably not be a big deal, but let's try to stick to it where possible). Can we figure out the Qualcomm questions before we check this in? As far as I'm aware this is their current draft patch: CB:57615. Does someone who understands PCIe better than I do follow what's going on there (is it really normal to run that much code for each register access)? Also, as far as I can see the mmio_size is set to 1MB in CB:61773, so I guess it's not always 4K?