[coreboot-gerrit] Change in coreboot[master]: AGESA, binaryPI: implement C bootblock

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36914 )

Change subject: AGESA, binaryPI: implement C bootblock
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Patch Set 30:

(1 comment)

https://review.coreboot.org/c/coreboot/+/36914/28/src/drivers/amd/agesa/boot... 
File src/drivers/amd/agesa/bootblock.c:

https://review.coreboot.org/c/coreboot/+/36914/28/src/drivers/amd/agesa/boot... 
PS28, Line 40: 	set_var_mtrr(mtrr, OPTIMAL_CACHE_ROM_BASE, OPTIMAL_CACHE_ROM_SIZE,
> Two quick questions. […]

The magic value should be in %edi, not %edx? It is to make CPU really respond to the rdmsr/wrmsr instruction. I guess at some point in time AMD wanted to keep those MSRs hidden. I did not check what CPU_ID_FEATURES_MSR and CPU_ID_EXT_FEATURES_MSR really do, but maybe they were not MTRR related. Other MSRs are manipulated with common wrmsr() without the magic.

As you can quess, most of this is copy-paste from early fam15 and we should not really trust existing code to be correct.