Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45889 )
Change subject: mb/google/volteer: Expand WP_RO region to 8MB in fmap ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45889/2/src/mainboard/google/voltee... File src/mainboard/google/volteer/chromeos.fmd:
https://review.coreboot.org/c/coreboot/+/45889/2/src/mainboard/google/voltee... PS2, Line 9: # SPI flash only the top 16MiB actually gets memory mapped.
That is correct, x86 only memory maps the top 16 MiB of SPI flash, so in this case RW_SECTION_A ends […]
+1 to what Julius and Tim said. The RW_SECTIONs need to stay above 16MiB so that they are memory mapped.
About reducing the RW sizes by 2MiB each - I think it might be really difficult given the size of CSME RW binary. Has any one actually performed an analysis of how much we are actually using in each of these sections and what the worst case sizes would be? Karthik put together a nice worksheet for JSL(dedede): https://docs.google.com/spreadsheets/d/1FtivbWNQ78ozU5b5Ds10q-jZ09jRfa8Qb5Gy.... We need something similar for TGL(volteer) as well to understand the actual usage.