Paul Menzel (paulepanter@users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3220
-gerrit
commit 63a0f2f0b6b1a3271e1d5bb9c3415d795f863edb Author: Paul Menzel paulepanter@users.sourceforge.net Date: Wed May 8 17:08:55 2013 +0200
Intel GM45, 945, Sandy Bridge: Unify `delay.c` and `udelay.c`
Use the same indentation, comment placement and spelling of words. Run `indent -linux …`.
Change-Id: Id5765c45b28058cdd50ee4c0a1fd9f645ad7f3f8 Signed-off-by: Paul Menzel paulepanter@users.sourceforge.net --- src/northbridge/intel/gm45/delay.c | 5 ++--- src/northbridge/intel/i945/udelay.c | 5 ++--- src/northbridge/intel/sandybridge/udelay.c | 4 ++-- 3 files changed, 6 insertions(+), 8 deletions(-)
diff --git a/src/northbridge/intel/gm45/delay.c b/src/northbridge/intel/gm45/delay.c index a861e25..0b5ecd9 100644 --- a/src/northbridge/intel/gm45/delay.c +++ b/src/northbridge/intel/gm45/delay.c @@ -24,7 +24,7 @@ #include "delay.h"
/** - * Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock + * Intel Core(tm) CPUs always run the TSC at the maximum possible CPU clock */ static void _udelay(const u32 us, const u32 numerator, const int total) { @@ -62,8 +62,7 @@ static void _udelay(const u32 us, const u32 numerator, const int total) msr = rdmsr(0x198); divisor = (msr.hi >> 8) & 0x1f;
- /* CPU clock is always a quarter. */ - d = ((fsb * divisor) / numerator) / 4; + d = ((fsb * divisor) / numerator) / 4; /* CPU clock is always a quarter. */
multiply_to_tsc(&tscd, us, d);
diff --git a/src/northbridge/intel/i945/udelay.c b/src/northbridge/intel/i945/udelay.c index 3d5d6c6..60ca9fb 100644 --- a/src/northbridge/intel/i945/udelay.c +++ b/src/northbridge/intel/i945/udelay.c @@ -24,7 +24,7 @@ #include <cpu/intel/speedstep.h>
/** - * Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock + * Intel Core(tm) CPUs always run the TSC at the maximum possible CPU clock */
void udelay(u32 us) @@ -63,7 +63,7 @@ void udelay(u32 us) msr = rdmsr(0x198); divisor = (msr.hi >> 8) & 0x1f;
- d = (fsb * divisor) / 4; /* CPU clock is always a quarter. */ + d = (fsb * divisor) / 4; /* CPU clock is always a quarter. */
multiply_to_tsc(&tscd, us, d);
@@ -79,5 +79,4 @@ void udelay(u32 us) tsc = rdtsc(); } while ((tsc.hi < tsc1.hi) || ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo))); - } diff --git a/src/northbridge/intel/sandybridge/udelay.c b/src/northbridge/intel/sandybridge/udelay.c index a2ce0d8..670898a 100644 --- a/src/northbridge/intel/sandybridge/udelay.c +++ b/src/northbridge/intel/sandybridge/udelay.c @@ -23,7 +23,7 @@ #include <cpu/x86/msr.h>
/** - * Intel SandyBridge/IvyBridge CPUs always run the TSC at BCLK=100MHz + * Intel Sandy Bridge/Ivy Bridge CPUs always run the TSC at BCLK=100MHz */
void udelay(u32 us) @@ -37,7 +37,7 @@ void udelay(u32 us) msr = rdmsr(0xce); divisor = (msr.lo >> 8) & 0xff;
- d = fsb * divisor; /* On Core/Core2 this is divided by 4 */ + d = fsb * divisor; /* On Core/Core2 this is divided by 4 */ multiply_to_tsc(&tscd, us, d);
tsc1 = rdtsc();