[coreboot-gerrit] [L] Change in coreboot[main]: soc/intel/xeon_sp: Redesign resource allocation

[Shuo Liu (Code Review)]

Attention is currently required from: Arthur Heymans, Christian Walter, David Hendricks, Felix Held, Nill Ge, Patrick Rudolph, TangYiwei, Tim Chu.

Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78327?usp=email )

Change subject: soc/intel/xeon_sp: Redesign resource allocation
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Patch Set 2:

(1 comment)

Patchset:

PS2: 
Hi, Arthur, we evaluated this CR and like the change. Here is some thoughts to sync with you and the loop.

1) We will move GNR codes based on this new design. Both GNR codes and your changes are based on multi-domain design, and hence theoretically they naturally and mutually fit. But GNR codes is based on FSP2.4 new IIO interface while SPR and previous gen are based on FSP2.3 or earlier, hence we need to seek some adoption logics to make the common codes to support both. For this, we could have separate discussion.

2) We evaluated this change on our SPR test machine and found that PCI resource setting is needed, otherwise, some legacy IO access (RTC, et al) might be mistakenly taken by BMC video device without BAR programed. This issue might not occur on every machine, but as a robustness enhancement, we suggest to take care in this CR as well.