Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35225 )
Change subject: soc/intel/common/block/cse: Move me_read_config32() to common code ......................................................................
Patch Set 7:
(35 comments)
https://review.coreboot.org/c/coreboot/+/35225/1/src/soc/intel/apollolake/cs... File src/soc/intel/apollolake/cse.c:
https://review.coreboot.org/c/coreboot/+/35225/1/src/soc/intel/apollolake/cs... PS1, Line 46:
use tab ?
Done
https://review.coreboot.org/c/coreboot/+/35225/1/src/soc/intel/common/block/... File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/35225/1/src/soc/intel/common/block/... PS1, Line 516: if (!CONFIG(CONSOLE_SERIAL))
Done
Done
https://review.coreboot.org/c/coreboot/+/35225/1/src/soc/intel/common/block/... PS1, Line 520: if( offset == PCI_ME_HFSTS1)
Done
Done
https://review.coreboot.org/c/coreboot/+/35225/1/src/soc/intel/common/block/... PS1, Line 520: if( offset == PCI_ME_HFSTS1)
Done
Done
https://review.coreboot.org/c/coreboot/+/35225/2/src/soc/intel/common/block/... File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/35225/2/src/soc/intel/common/block/... PS2, Line 518: index = 1
Done
Done
https://review.coreboot.org/c/coreboot/+/35225/3/src/soc/intel/common/block/... File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/35225/3/src/soc/intel/common/block/... PS3, Line 564: if (offset == PCI_ME_HFSTS1)
trailing whitespace
Done
https://review.coreboot.org/c/coreboot/+/35225/4/src/soc/intel/common/block/... File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/35225/4/src/soc/intel/common/block/... PS4, Line 525: if (index != 0) {
braces {} are not necessary for any arm of this statement
Done
https://review.coreboot.org/c/coreboot/+/35225/4/src/soc/intel/common/block/... PS4, Line 538: if (!CONFIG(CONSOLE_SERIAL)) {
braces {} are not necessary for single statement blocks
Done
https://review.coreboot.org/c/coreboot/+/35225/5/src/soc/intel/common/block/... File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/35225/5/src/soc/intel/common/block/... PS5, Line 511: if (offset == PCI_ME_HFSTS1) {
Done
Done
https://review.coreboot.org/c/coreboot/+/35225/5/src/soc/intel/common/block/... PS5, Line 514: else if (offset == PCI_ME_HFSTS2) {
Done
Done
https://review.coreboot.org/c/coreboot/+/35225/5/src/soc/intel/common/block/... PS5, Line 517: else if (offset == PCI_ME_HFSTS3) {
Done
Done
https://review.coreboot.org/c/coreboot/+/35225/5/src/soc/intel/common/block/... PS5, Line 523: else if (offset == PCI_ME_HFSTS5) {
Done
Done
https://review.coreboot.org/c/coreboot/+/35225/5/src/soc/intel/common/block/... PS5, Line 526: else if (offset == PCI_ME_HFSTS6) {
Done
Done
https://review.coreboot.org/c/coreboot/+/35225/5/src/soc/intel/common/block/... PS5, Line 529: else {
Done
Done
https://review.coreboot.org/c/coreboot/+/35225/5/src/soc/intel/common/block/... PS5, Line 533: if (index != 0) {
Done
Done
https://review.coreboot.org/c/coreboot/+/35225/5/src/soc/intel/common/block/... PS5, Line 546: if (!CONFIG(CONSOLE_SERIAL)) {
Done
Done
https://review.coreboot.org/c/coreboot/+/35225/6/src/soc/intel/common/block/... File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/35225/6/src/soc/intel/common/block/... PS6, Line 540:
trailing whitespace
Done
https://review.coreboot.org/c/coreboot/+/35225/3/src/soc/intel/common/block/... File src/soc/intel/common/block/include/intelblocks/cse.h:
https://review.coreboot.org/c/coreboot/+/35225/3/src/soc/intel/common/block/... PS3, Line 62: <<<<<<< HEAD
spaces required around that '<' (ctx:OxW)
Done
https://review.coreboot.org/c/coreboot/+/35225/3/src/soc/intel/common/block/... PS3, Line 65: =======
spaces required around that '==' (ctx:OxO)
Done
https://review.coreboot.org/c/coreboot/+/35225/3/src/soc/intel/common/block/... PS3, Line 65: =======
spaces required around that '=' (ctx:OxE)
Done
https://review.coreboot.org/c/coreboot/+/35225/3/src/soc/intel/common/block/... PS3, Line 65: =======
spaces required around that '==' (ctx:OxO)
Done
https://review.coreboot.org/c/coreboot/+/35225/3/src/soc/intel/common/block/... PS3, Line 65: =======
spaces required around that '==' (ctx:ExO)
Done
https://review.coreboot.org/c/coreboot/+/35225/3/src/soc/intel/common/block/... PS3, Line 79: >>>>>>> b2d10c8321... src/soc/intel/common/block/cse: Add helper functions to CSE lib
spaces required around that ':' (ctx:VxW)
Done
https://review.coreboot.org/c/coreboot/+/35225/3/src/soc/intel/common/block/... PS3, Line 79: >>>>>>> b2d10c8321... src/soc/intel/common/block/cse: Add helper functions to CSE lib
spaces required around that '>' (ctx:OxW)
Done
https://review.coreboot.org/c/coreboot/+/35225/2/src/soc/intel/common/block/... File src/soc/intel/common/block/include/intelblocks/cse.h:
https://review.coreboot.org/c/coreboot/+/35225/2/src/soc/intel/common/block/... PS2, Line 62:
Done
Done
https://review.coreboot.org/c/coreboot/+/35225/1/src/soc/intel/common/block/... File src/soc/intel/common/block/include/intelblocks/cse.h:
https://review.coreboot.org/c/coreboot/+/35225/1/src/soc/intel/common/block/... PS1, Line 67: PCI_ME_HFSTS1 = 0x40,
Done
Done
https://review.coreboot.org/c/coreboot/+/35225/1/src/soc/intel/common/block/... PS1, Line 67: PCI_ME_HFSTS1 = 0x40,
Done
Done
https://review.coreboot.org/c/coreboot/+/35225/1/src/soc/intel/common/block/... PS1, Line 68: PCI_ME_HFSTS2 = 0x48,
Done
Done
https://review.coreboot.org/c/coreboot/+/35225/1/src/soc/intel/common/block/... PS1, Line 68: PCI_ME_HFSTS2 = 0x48,
Done
Done
https://review.coreboot.org/c/coreboot/+/35225/1/src/soc/intel/common/block/... PS1, Line 69: PCI_ME_HFSTS3 = 0x60,
Done
Done
https://review.coreboot.org/c/coreboot/+/35225/1/src/soc/intel/common/block/... PS1, Line 69: PCI_ME_HFSTS3 = 0x60,
Done
Done
https://review.coreboot.org/c/coreboot/+/35225/1/src/soc/intel/common/block/... PS1, Line 70: PCI_ME_HFSTS4 = 0x64,
Done
Done
https://review.coreboot.org/c/coreboot/+/35225/1/src/soc/intel/common/block/... PS1, Line 70: PCI_ME_HFSTS4 = 0x64,
code indent should use tabs where possible
Done
https://review.coreboot.org/c/coreboot/+/35225/1/src/soc/intel/common/block/... PS1, Line 71: PCI_ME_HFSTS5 = 0x68,
Done
Done
https://review.coreboot.org/c/coreboot/+/35225/1/src/soc/intel/common/block/... PS1, Line 72: PCI_ME_HFSTS6 = 0x6C,
Done
Done