[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake/romstage: Skip GPIO configuration from FSP

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46696 )

Change subject: soc/intel/alderlake/romstage: Skip GPIO configuration from FSP
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soc/intel/alderlake/romstage: Skip GPIO configuration from FSP

Set GpioOverride UPD to 1 to skip GPIO configuration in FSP phases

TEST=Able to build and boot ADLRVP to OS.

Change-Id: Ie965a85d9da9b6a23b385536313b852e66909cf4
Signed-off-by: Subrata Banik 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46696
Tested-by: build bot (Jenkins) 
Reviewed-by: Angel Pons 
Reviewed-by: Furquan Shaikh 
---
M src/soc/intel/alderlake/romstage/fsp_params.c
1 file changed, 3 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved
  Angel Pons: Looks good to me, approved

diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index 38c1a1b..868d75e 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -157,6 +157,9 @@
    m_cfg->CpuPcieRpEnableMask = is_dev_enabled(dev);

m_cfg->TmeEnable = CONFIG(INTEL_TME);
+
+	/* Skip GPIO configuration from FSP */
+	m_cfg->GpioOverride = 0x1;
 }

void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)