[coreboot-gerrit] Change in coreboot[master]: soc/intel/denverton_ns/bootblock: Fix 32-bit RW PCI_BASE_ADDRESS_0 re...

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41609 )

Change subject: soc/intel/denverton_ns/bootblock: Fix 32-bit RW PCI_BASE_ADDRESS_0 register
......................................................................

soc/intel/denverton_ns/bootblock: Fix 32-bit RW PCI_BASE_ADDRESS_0 register

Change-Id: I2b65b2aee672808932e32438410a4ebe8fa37606
Signed-off-by: Elyes HAOUAS 
---
M src/soc/intel/denverton_ns/bootblock/uart.c
1 file changed, 1 insertion(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/41609/1

diff --git a/src/soc/intel/denverton_ns/bootblock/uart.c b/src/soc/intel/denverton_ns/bootblock/uart.c
index 7514fee..78018ca 100644
--- a/src/soc/intel/denverton_ns/bootblock/uart.c
+++ b/src/soc/intel/denverton_ns/bootblock/uart.c
@@ -17,15 +17,13 @@
 static void pci_early_hsuart_device_probe(u8 bus, u8 dev, u8 func,
    				  u32 mmio_base)
 {
-	register uint16_t reg16;
    pci_devfn_t uart_dev = PCI_DEV(bus, dev, func);

/* We're using MMIO for HSUARTs. This section is needed for logging
    *  from FSP only
    */
    /* Decode IOBASE at IOBA (BAR0). */
-	reg16 = pci_read_config16(uart_dev, PCI_BASE_ADDRESS_0) | mmio_base;
-	pci_write_config16(uart_dev, PCI_BASE_ADDRESS_0, reg16);
+	pci_or_config32(uart_dev, PCI_BASE_ADDRESS_0, mmio_base);

#if (CONFIG(NON_LEGACY_UART_MODE))
    /* Decode MMIO at MEMBA (BAR1) */