[coreboot-gerrit] [S] Change in coreboot[main]: soc/mediatek/mt8189: Reduce bootblock size by separating SPI NOR GPIOs

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change by Vince Liu. ( https://review.coreboot.org/c/coreboot/+/86538?usp=email )

Change subject: soc/mediatek/mt8189: Reduce bootblock size by separating SPI NOR GPIOs
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Patch Set 4:

(1 comment)

File src/soc/mediatek/mt8189/gpio.c:

https://review.coreboot.org/c/coreboot/+/86538/comment/117311a6_083030fe?usp... :
PS4, Line 23: [SPI_NOR_CK] = { 0x10, 12, 3, },
            : 	[SPI_NOR_CS] = { 0x10, 27, 3, },
            : 	[SPI_NOR_IO0] = { 0x10, 15, 3, },
            : 	[SPI_NOR_IO1] = { 0x10, 18, 3, },
            : 	[SPI_NOR_IO2] = { 0x10, 21, 3, },
            : 	[SPI_NOR_IO3] = { 0x10, 24, 3, },
A comment would have been nice, that to compare the tables SPI_NOR_GPIO_BASE has to be added.