Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35638 )
Change subject: mb/google/drallion: Configure LPSS controller parameters ......................................................................
mb/google/drallion: Configure LPSS controller parameters
drallion uses below LPSS controllers:
I2C: 0/1/4 GSPI: None UART: 0(Console)
BUG=b:141575294
Change-Id: I9c57f8054f5da5add667168502ebc3e089c440f8 Signed-off-by: Aamir Bohra aamir.bohra@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/35638 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Bora Guvendik bora.guvendik@intel.com --- M src/mainboard/google/drallion/variants/drallion/devicetree.cb 1 file changed, 15 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Bora Guvendik: Looks good to me, approved
diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 956e54e..2e8edd5 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -13,6 +13,21 @@ register "gen2_dec" = "0x00040941" # 0x940-0x947 register "gen3_dec" = "0x000c0951" # 0x950-0x95f
+ register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, + [PchSerialIoIndexSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexSPI1] = PchSerialIoDisabled, + [PchSerialIoIndexSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + # FSP configuration register "SaGv" = "SaGv_Enabled" register "HeciEnabled" = "0"