[coreboot-gerrit] Change in coreboot[master]: src/soc/tigerlake: Add memory configuration support for Jasper Lake

[Karthik Ramasubramanian (Code Review)]

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39135 )

Change subject: src/soc/tigerlake: Add memory configuration support for Jasper Lake
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Patch Set 18:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39135/14/src/soc/intel/tigerlake/in... 
File src/soc/intel/tigerlake/include/soc/meminit_jsl.h:

https://review.coreboot.org/c/coreboot/+/39135/14/src/soc/intel/tigerlake/in... 
PS14, Line 132: )
> I second Subrata. […]

What if only 2 of the 4 LPDDR4x memory components/slots are populated. Currently we have a strap to identify the number of memory slots populated. For example in CNL, spd[2] is filled if the concerned slot is populated and MemorySpdPtr10 UPD is filled in accordingly. Please bear with me if I am butchering the terminologies.