[coreboot-gerrit] [XS] Change in coreboot[main]: mb/google/nissa/var/pujjoga: Disable pcie_RP7 setting for S0ix problem

[Roger Wang (Code Review)]

Roger Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83058?usp=email )

Change subject: mb/google/nissa/var/pujjoga: Disable pcie_RP7 setting for S0ix problem
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mb/google/nissa/var/pujjoga: Disable pcie_RP7 setting for S0ix problem

Disable pcie_RP7 setting to modify system enter S0ix  problem on pujjoga

BUG=b:335312655
TEST=Build and check S0ix function and verify FAFT sleep funciton.

Change-Id: I7918e26fe382d4d9992a0e2744a2f8894a070e36
Signed-off-by: Roger Wang 
---
M src/mainboard/google/brya/variants/pujjoga/overridetree.cb
1 file changed, 1 insertion(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/83058/1

diff --git a/src/mainboard/google/brya/variants/pujjoga/overridetree.cb b/src/mainboard/google/brya/variants/pujjoga/overridetree.cb
index 951d60e..8b736d6 100644
--- a/src/mainboard/google/brya/variants/pujjoga/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjoga/overridetree.cb
@@ -307,6 +307,7 @@
    			device pci 00.0 on end
    		end
    	end
+		device ref pcie_rp7 off end
    	device ref pch_espi on
    		chip ec/google/chromeec
    			use conn0 as mux_conn[0]