[coreboot-gerrit] [S] Change in coreboot[main]: soc/intel/xeon_sp: Add fix for DPR silicon bug

[Patrick Rudolph (Code Review)]

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Shuo Liu, Tim Chu, Vasiliy Khoruzhick, [e-mail].

Patrick Rudolph has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85829?usp=email )

Change subject: soc/intel/xeon_sp: Add fix for DPR silicon bug
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Patch Set 2:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/85829/comment/2af0bf82_731dd181?usp... :
PS1, Line 16: On previous CPUs and newer CPUs the assumption is still correct and
> The assumption is that DRP TOP bits are never read as 0, as this sentence is stating. […]

Done