Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41155 )
Change subject: soc/intel/common/block/systemagent: Use TOUUD as base for MMIO above 4G ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41155/2/src/soc/intel/common/block/... File src/soc/intel/common/block/systemagent/systemagent.c:
https://review.coreboot.org/c/coreboot/+/41155/2/src/soc/intel/common/block/... PS2, Line 118: if (!get_enable_above_4GB_mmio())
That is what I am trying to track down. I found this CL from Subrata: https://review.coreboot. […]
while enabling DGPU with coreboot and chrome, i have seen that device with higher memory requirement might try to access > 4GB memory. And causing such issue when Above 4GB base and limit size is incorrect.
Unable to boot with dGPU on IA platform with below error:
[ 2.297425] pcieport 0000:00:1c.0: PCI bridge to [bus 05] [ 2.302858] pcieport 0000:00:1c.0: bridge window [io 0x2000-0x2fff] [ 2.309427] pcieport 0000:00:1c.0: bridge window [mem 0xb2000000-0xb20fffff] [ 2.316679] pcieport 0000:00:1c.0: bridge window [mem 0x840000000-0x8c01fffff 64bit pref] [ 2.325072] pcieport 0000:00:1c.0: PCI bridge to [bus 05] [ 2.330502] pcieport 0000:00:1c.0: bridge window [io 0x2000-0x2fff] [ 2.337062] pcieport 0000:00:1c.0: bridge window [mem 0xb2000000-0xb20fffff] [ 2.344317] pcieport 0000:00:1c.0: bridge window [mem 0xa0000000-0xb01fffff 64bit pref] [ 2.352541] [drm] Not enough PCI address space for a large BAR.
After making sure we have right base and limit like below CL, we don't see such issue as mentioned above.
https://review.coreboot.org/c/coreboot/+/38125/10/src/soc/intel/cannonlake/i...
Also i could see an FSP UPD which does some additional programming if we like to enable memory above 4GB.
https://github.com/otcshare/CCG-TGL-Generic-SiC/blob/master/TigerLakeFspPkg/...