Martin Roth has posted comments on this change. ( https://review.coreboot.org/19960 )
Change subject: nb/sandybridge:add CBMEM_MEMINFO table when initing RAM ......................................................................
Patch Set 1:
(4 comments)
https://review.coreboot.org/#/c/19960/1/src/northbridge/intel/sandybridge/ra... File src/northbridge/intel/sandybridge/raminit_mrc.c:
PS1, Line 308: 0x5e04 MC_BIOS_DATA in northbridge/intel/sandybridge/raminit_common.h?
I guess none of the other MCHBAR values are defined anywhere, so maybe that doesn't make sense.
PS1, Line 310: addr_decode_ch This looks like channels, but we can have two dimms per channel, so should this be multiplied by 2, or should we have a j loop?
PS1, Line 325: 122 Hrm - looks like we need an spd_ddr3.h file.
PS1, Line 328: same for all modules so use first what if not all modules are populated?