[coreboot-gerrit] [S] Change in coreboot[main]: mb/google/fatcat: Move Finger Print Sensor (FPS) from GSPI0A to GSPI0

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86143?usp=email )

(

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: mb/google/fatcat: Move Finger Print Sensor (FPS) from GSPI0A to GSPI0
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mb/google/fatcat: Move Finger Print Sensor (FPS) from GSPI0A to GSPI0

This moves the FPS device from GSPI0A to GSPI0 to align with the
hardware design dated Jan'25.

The FPS device was initially placed on GSPI0A, which was incorrect. This
commit rectifies the configuration by moving it to the correct GSPI0
interface.

This change ensures that the CRFP device is correctly connected and
functions as expected.

BUG=b:377595986
TEST=Able to build and boot google/fatcat.

Change-Id: I3996f1a054204689ad733c650b6f71f1482c0b22
Signed-off-by: Subrata Banik 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86143
Reviewed-by: Paul Menzel 
Reviewed-by: Pranava Y N 
Reviewed-by: Kapil Porwal 
Reviewed-by: Jayvik Desai 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
1 file changed, 20 insertions(+), 20 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Kapil Porwal: Looks good to me, approved
  Pranava Y N: Looks good to me, approved
  Paul Menzel: Looks good to me, but someone else must approve
  Jayvik Desai: Looks good to me, approved

diff --git a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
index 5414e15..cb4c21a 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
@@ -108,9 +108,9 @@
    }"

register "serial_io_gspi_mode" = "{
-		[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
+		[PchSerialIoIndexGSPI0] = PchSerialIoPci,
    	[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
-		[PchSerialIoIndexGSPI0A] = PchSerialIoPci,
+		[PchSerialIoIndexGSPI0A] = PchSerialIoDisabled,
    }"

# Intel Common SoC Config
@@ -395,24 +395,6 @@
    		end
    	end

-		device ref gspi0a on
-			chip drivers/spi/acpi
-				register "name" = ""CRFP""
-				register "hid" = "ACPI_DT_NAMESPACE_HID"
-				register "uid" = "1"
-				register "compat_string" = ""google,cros-ec-spi""
-				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_D01_IRQ)"
-				register "wake" = "GPE0_DW1_01"
-				register "has_power_resource" = "true"
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C15)"
-				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E19)"
-				register "enable_delay_ms" = "3"
-				device spi 0 on
-					probe FP FP_PRESENT
-				end
-			end # FPMCU
-		end
-
    	device ref xhci on
    		chip drivers/usb/acpi
    			device ref xhci_root_hub on
@@ -850,6 +832,24 @@
    		end
    	end # I2C5

+		device ref gspi0 on
+			chip drivers/spi/acpi
+				register "name" = ""CRFP""
+				register "hid" = "ACPI_DT_NAMESPACE_HID"
+				register "uid" = "1"
+				register "compat_string" = ""google,cros-ec-spi""
+				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_D01_IRQ)"
+				register "wake" = "GPE0_DW1_01"
+				register "has_power_resource" = "true"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C15)"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E19)"
+				register "enable_delay_ms" = "3"
+				device spi 0 on
+					probe FP FP_PRESENT
+				end
+			end # FPMCU
+		end
+
    	device ref smbus on end
    	device ref npk on end
    	device ref hda on