HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41943 )
Change subject: sb/intel/lynxpoint: Clean up code ......................................................................
Patch Set 3: Code-Review+1
(8 comments)
https://review.coreboot.org/c/coreboot/+/41943/3/src/southbridge/intel/lynxp... File src/southbridge/intel/lynxpoint/azalia.c:
https://review.coreboot.org/c/coreboot/+/41943/3/src/southbridge/intel/lynxp... PS3, Line 141: what is the rule here? tab or whitespace :p
https://review.coreboot.org/c/coreboot/+/41943/3/src/southbridge/intel/lynxp... File src/southbridge/intel/lynxpoint/elog.c:
https://review.coreboot.org/c/coreboot/+/41943/3/src/southbridge/intel/lynxp... PS3, Line 33: :)
https://review.coreboot.org/c/coreboot/+/41943/3/src/southbridge/intel/lynxp... File src/southbridge/intel/lynxpoint/hda_verb.c:
https://review.coreboot.org/c/coreboot/+/41943/3/src/southbridge/intel/lynxp... PS3, Line 147: // in u32 maybe drop
https://review.coreboot.org/c/coreboot/+/41943/3/src/southbridge/intel/lynxp... File src/southbridge/intel/lynxpoint/lpc.c:
https://review.coreboot.org/c/coreboot/+/41943/3/src/southbridge/intel/lynxp... PS3, Line 257: ~(7 << 10) use macro and remove the comment ?
https://review.coreboot.org/c/coreboot/+/41943/3/src/southbridge/intel/lynxp... PS3, Line 258: 1 << 0) use macro and remove the comment ?
https://review.coreboot.org/c/coreboot/+/41943/3/src/southbridge/intel/lynxp... File src/southbridge/intel/lynxpoint/sata.c:
https://review.coreboot.org/c/coreboot/+/41943/3/src/southbridge/intel/lynxp... PS3, Line 314: someone else will use tabs...
https://review.coreboot.org/c/coreboot/+/41943/3/src/southbridge/intel/lynxp... File src/southbridge/intel/lynxpoint/serialio.c:
https://review.coreboot.org/c/coreboot/+/41943/3/src/southbridge/intel/lynxp... PS3, Line 224: someone else will use tabs. I think we need a rule for this
https://review.coreboot.org/c/coreboot/+/41943/3/src/southbridge/intel/lynxp... File src/southbridge/intel/lynxpoint/smbus.c:
https://review.coreboot.org/c/coreboot/+/41943/3/src/southbridge/intel/lynxp... PS3, Line 54: why?