Hello Edward O'Callaghan,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/37591
to review the following change.
Change subject: mb/google/hatch/variant/hatch: Config MEM_STRAP GPIOs ......................................................................
mb/google/hatch/variant/hatch: Config MEM_STRAP GPIOs
Hatch always used the default MEM_STRAPs in baseboard. Adding explicit configuration for the Hatch variant in the event that MEM_STRAP is set differently in the baseboard gpio file.
BUG=b:144895517 BRANCH=hatch TEST=./util/abuild/abuild -p none -t google/hatch -x -a
Change-Id: I6f6cb0af2d159ba9532f413939b546526b64a935 Signed-off-by: Edward O'Callaghan quasisec@google.com --- M src/mainboard/google/hatch/variants/hatch/gpio.c 1 file changed, 10 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/37591/1
diff --git a/src/mainboard/google/hatch/variants/hatch/gpio.c b/src/mainboard/google/hatch/variants/hatch/gpio.c index 56f587b..9aac509 100644 --- a/src/mainboard/google/hatch/variants/hatch/gpio.c +++ b/src/mainboard/google/hatch/variants/hatch/gpio.c @@ -20,7 +20,16 @@
static const struct pad_config gpio_table[] = { /* C13 : EC_PCH_INT_L */ - PAD_CFG_GPI_APIC(GPP_C13, UP_20K, PLTRST, LEVEL, INVERT)}; + PAD_CFG_GPI_APIC(GPP_C13, UP_20K, PLTRST, LEVEL, INVERT), + /* F11 : PCH_MEM_STRAP2 */ + PAD_CFG_GPI(GPP_F11, NONE, PLTRST), + /* F20 : PCH_MEM_STRAP0 */ + PAD_CFG_GPI(GPP_F20, NONE, PLTRST), + /* F21 : PCH_MEM_STRAP1 */ + PAD_CFG_GPI(GPP_F21, NONE, PLTRST), + /* F22 : PCH_MEM_STRAP3 */ + PAD_CFG_GPI(GPP_F22, NONE, PLTRST), +};
const struct pad_config *override_gpio_table(size_t *num) {