EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32519
Change subject: mb/google/sarien: Turn off camera power when s0ix ......................................................................
mb/google/sarien: Turn off camera power when s0ix
Turn off camera power when s0ix for power saving. ACPI _ON/_OFF is not taken by UVC driver, so invoke s0ix method from LPIT.
BUG=b:129177593 TEST= measure camera power comsumption is 0mV under s0ix
Change-Id: I5a9b7ec1e95cc9931d8d5f2dc1254805c9d0ffed Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com --- M src/mainboard/google/sarien/dsdt.asl A src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl A src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl M src/soc/intel/cannonlake/acpi/lpit.asl 4 files changed, 62 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/32519/1
diff --git a/src/mainboard/google/sarien/dsdt.asl b/src/mainboard/google/sarien/dsdt.asl index e5b0cca..58e0704 100644 --- a/src/mainboard/google/sarien/dsdt.asl +++ b/src/mainboard/google/sarien/dsdt.asl @@ -40,6 +40,8 @@ #include <soc/intel/cannonlake/acpi/northbridge.asl> #include <soc/intel/cannonlake/acpi/southbridge.asl> } + /* Per board variant mainboard hooks. */ + #include <variant/acpi/mainboard.asl> }
#if CONFIG(CHROMEOS) diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000..7c22710 --- /dev/null +++ b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define CAM_EN GPP_B11 + +/* Method called from LPIT prior to enter s0ix state */ +Method (MS0X, 1) { + If (Arg0) { + Printf ("OS Enter S0ix") + /* Turn on camera power */ + _SB.PCI0.STXS (GPP_B11) + } Else { + Printf ("OS Exit S0ix") + /* Turn off camera power */ + _SB.PCI0.CTXS (GPP_B11) + } +} diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000..7c22710 --- /dev/null +++ b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define CAM_EN GPP_B11 + +/* Method called from LPIT prior to enter s0ix state */ +Method (MS0X, 1) { + If (Arg0) { + Printf ("OS Enter S0ix") + /* Turn on camera power */ + _SB.PCI0.STXS (GPP_B11) + } Else { + Printf ("OS Exit S0ix") + /* Turn off camera power */ + _SB.PCI0.CTXS (GPP_B11) + } +} diff --git a/src/soc/intel/cannonlake/acpi/lpit.asl b/src/soc/intel/cannonlake/acpi/lpit.asl index 8515806..00115a5 100644 --- a/src/soc/intel/cannonlake/acpi/lpit.asl +++ b/src/soc/intel/cannonlake/acpi/lpit.asl @@ -62,12 +62,14 @@ */ If(Arg2 == 5) { _SB.PCI0.LPCB.EC0.S0IX(1) + _SB.MS0X(1) } /* * Function 6. */ If(Arg2 == 6) { _SB.PCI0.LPCB.EC0.S0IX(0) + _SB.MS0X(0) } } Return(Buffer(One) {0x00})