[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Speed up postcar loading using intermediate cac...

[Subrata Banik (Code Review)]

Hello Aaron Durbin, Patrick Rudolph, Aamir Bohra, Paul Menzel, Duncan Laurie, V Sowmya, build bot (Jenkins), Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/34791

to look at the new patch set (#4).

Change subject: soc/intel/cannonlake: Speed up postcar loading using intermediate caching
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soc/intel/cannonlake: Speed up postcar loading using intermediate caching

This patch ensures intermediate caching is enabled to speed up
loading and decompression of next stage as we are still in romstage
and CAR tear down will be handled by next stage at its entry.

TEST=cbmem -t shows ~3-5ms time savings in warm reboot case with this
CL on CML-Hatch.

Change-Id: I3ba63887acb5c4bdeaf3e21c24fb0e631362962c
Signed-off-by: Subrata Banik 
---
M src/soc/intel/cannonlake/romstage/romstage.c
1 file changed, 27 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/34791/4