[coreboot-gerrit] [M] Change in coreboot[main]: soc/intel/cse: Implement APIs to access PSR backup status in CMOS

[Anil Kumar K (Code Review)]

Attention is currently required from: Jérémy Compostella, Krishna P Bhat D, Rizwan Qureshi, Subrata Banik, sridhar siricilla.

Anil Kumar K has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77069?usp=email )

Change subject: soc/intel/cse: Implement APIs to access PSR backup status in CMOS
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Patch Set 7:

(1 comment)

File src/soc/intel/common/block/include/intelblocks/cse.h:

https://review.coreboot.org/c/coreboot/+/77069/comment/aa7c53ea_8017584e :
PS5, Line 171: 0x55
> > No specific meaning, this value is chosen by us. […]

Hi Subrata , We kept the values 0x55 and 0x22 to make sure these are not commonly occuring values like 0/1 . So we suggest to have them 0x55/0x22 to ensure it doesn't coincide with default cmos values during bootup