[coreboot-gerrit] Change in coreboot[master]: sb/intel/lynxpoint: Set PCIe L1 substate capabilities register

[Matt DeVillier (Code Review)]

Hello build bot (Jenkins), Angel Pons, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/46134

to look at the new patch set (#2).

Change subject: sb/intel/lynxpoint: Set PCIe L1 substate capabilities register
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sb/intel/lynxpoint: Set PCIe L1 substate capabilities register

Copied from soc/intel/broadwell.

Test: build/boot google/beltino variants

Change-Id: Ib2ae3d9539de9f7e22975f00450d9d60d1fd938a
Signed-off-by: Matt DeVillier 
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M src/southbridge/intel/lynxpoint/pcie.c
1 file changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/46134/2