Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58998 )
Change subject: google/beltino,jecht: Refactor ChromeOS GPIOs ......................................................................
google/beltino,jecht: Refactor ChromeOS GPIOs
Change-Id: I4052baca2d8041b2a6d6fd410fcf99248662d7a5 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/mainboard/google/beltino/chromeos.c M src/mainboard/google/beltino/onboard.h M src/mainboard/google/jecht/chromeos.c M src/mainboard/google/jecht/onboard.h 4 files changed, 37 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/58998/1
diff --git a/src/mainboard/google/beltino/chromeos.c b/src/mainboard/google/beltino/chromeos.c index 6ed8e3a..2d35e75 100644 --- a/src/mainboard/google/beltino/chromeos.c +++ b/src/mainboard/google/beltino/chromeos.c @@ -8,9 +8,7 @@ #include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/common/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> - -#define GPIO_SPI_WP 58 -#define GPIO_REC_MODE 12 +#include "onboard.h"
#define FLAG_SPI_WP 0 #define FLAG_REC_MODE 1 @@ -27,6 +25,16 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); }
+static bool raw_write_protect_state(void) +{ + return get_gpio(GPIO_SPI_WP); +} + +static bool raw_recovery_mode_switch(void) +{ + return !get_gpio(GPIO_REC_MODE); +} + int get_write_protect_state(void) { const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); @@ -45,11 +53,11 @@ const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
/* Write Protect: GPIO58 = GPIO_SPI_WP, active high */ - if (get_gpio(GPIO_SPI_WP)) + if (raw_write_protect_state()) flags |= (1 << FLAG_SPI_WP);
/* Recovery: GPIO12 = RECOVERY_L, active low */ - if (!get_gpio(GPIO_REC_MODE)) + if (raw_recovery_mode_switch()) flags |= (1 << FLAG_REC_MODE);
/* Developer: Virtual */ diff --git a/src/mainboard/google/beltino/onboard.h b/src/mainboard/google/beltino/onboard.h index 2cced23..8bd21ce 100644 --- a/src/mainboard/google/beltino/onboard.h +++ b/src/mainboard/google/beltino/onboard.h @@ -16,6 +16,12 @@ /* WLAN wake is GPIO 10 */ #define WLAN_WAKE_GPIO 10
+/* Recovery: GPIO12 = RECOVERY_L, active low */ +#define GPIO_REC_MODE 12 + +/* Write Protect: GPIO58 = GPIO_SPI_WP, active high */ +#define GPIO_SPI_WP 58 + /* IT8772F defs */ #define IT8772F_BASE 0x2e #define IT8772F_SERIAL_DEV PNP_DEV(IT8772F_BASE, IT8772F_SP1) diff --git a/src/mainboard/google/jecht/chromeos.c b/src/mainboard/google/jecht/chromeos.c index 70bc5d7..4588e31 100644 --- a/src/mainboard/google/jecht/chromeos.c +++ b/src/mainboard/google/jecht/chromeos.c @@ -12,9 +12,6 @@ #include <southbridge/intel/lynxpoint/lp_gpio.h> #include "onboard.h"
-#define GPIO_SPI_WP 58 -#define GPIO_REC_MODE 12 - #define FLAG_SPI_WP 0 #define FLAG_REC_MODE 1
@@ -30,6 +27,16 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); }
+static bool raw_write_protect_state(void) +{ + return get_gpio(GPIO_SPI_WP); +} + +static bool raw_recovery_mode_switch(void) +{ + return !get_gpio(GPIO_REC_MODE); +} + int get_write_protect_state(void) { const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); @@ -48,11 +55,11 @@ const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
/* Write Protect: GPIO58 = GPIO_SPI_WP, active high */ - if (get_gpio(GPIO_SPI_WP)) + if (raw_write_protect_state()) flags |= (1 << FLAG_SPI_WP);
/* Recovery: GPIO12 = RECOVERY_L, active low */ - if (!get_gpio(GPIO_REC_MODE)) + if (raw_recovery_mode_switch()) flags |= (1 << FLAG_REC_MODE);
/* Developer: Virtual */ diff --git a/src/mainboard/google/jecht/onboard.h b/src/mainboard/google/jecht/onboard.h index 1c37d72..a6ba80a 100644 --- a/src/mainboard/google/jecht/onboard.h +++ b/src/mainboard/google/jecht/onboard.h @@ -37,4 +37,10 @@ #define IT8772F_GPIO_DEV PNP_DEV(IT8772F_BASE, IT8772F_GPIO) #define IT8772F_SUPERIO_DEV PNP_DEV(IT8772F_BASE, 0)
+/* Write Protect: GPIO58 = GPIO_SPI_WP, active high */ +#define GPIO_SPI_WP 58 + +/* Recovery: GPIO12 = RECOVERY_L, active low */ +#define GPIO_REC_MODE 12 + #endif