Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33767 )
Change subject: soc/amd/picasso: Update UARTs ......................................................................
Patch Set 13:
(1 comment)
https://review.coreboot.org/c/coreboot/+/33767/13/src/soc/amd/picasso/includ... File src/soc/amd/picasso/include/soc/iomap.h:
https://review.coreboot.org/c/coreboot/+/33767/13/src/soc/amd/picasso/includ... PS13, Line 31: 0xfed80000 Thanks. Looking through a number of old specs, trying to determine when it showed up, was it a typo, etc., here's what I've come up with. The lowest offset for any of those registers is 0x40 (depending on the product).
FWIW, I'd compared the MMIO version with the D14F0 header before making the change. It looks like there are no definitions for D14F0x40-D14F0xFB. Looking more closely, I've used HDT to try to determine how much of D14F0 responds or is sticky from 0-FF. It's not much, so I suspect the majority of locations are unimplemented vs. undocumented. Also, this matches perfectly the behavior I see at 0xfed80000. Also, at 0xfed80040-50 I can see the USB registers.
In other words, I get 100% of the implemented D14F0 space at 0xfed80000, and I additionally get a handful of USB registers at 0xfed80040. Most importantly, part of that 100% is the UART Control register at 0xfc.
...and two BARs for SMBus and ASF...
FYI, the ST BKDG isn't as clear as the PCO PPR, so that I said wasn't correct about the BARs. These are read-only and are 0. In addition to the AcpiMmio ranges, SMBus and ASF controllers may also be accessed w/IO based on PMx00[15:8] when enabled.