Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34791 )
Change subject: soc/intel/cannonlake: Speed up postcar loading using intermediate caching ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34791/5/src/soc/intel/cannonlake/ro... File src/soc/intel/cannonlake/romstage/romstage.c:
https://review.coreboot.org/c/coreboot/+/34791/5/src/soc/intel/cannonlake/ro... PS5, Line 177: enable_ramstage_caching(top_of_ram, top_of_ram_size);
Do we want to add this as an option to postcar api?
that should be ideal but how do we know which MTRR is runtime MTRR and need to program before loading postcar stage? Because when control reaches postcar, inside postcar_frame we have multiple MTRR base and size, there is no such order to tell that index[0] is the one what i have to set before loading posrcar.
Basically provide a runtime mtrr option to be applied prior to loading?
Also changing postcar API might require to modify all SOC romstage.c code.