[coreboot-gerrit] Change in coreboot[master]: soc/intel/xeon_sp: update DIMM_MAX and DIMM_SPD_SIZE

[Jonathan Zhang (Code Review)]

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43982 )

Change subject: soc/intel/xeon_sp: update DIMM_MAX and DIMM_SPD_SIZE
......................................................................

soc/intel/xeon_sp: update DIMM_MAX and DIMM_SPD_SIZE

SKX-SP and CPX-SP processors have 2 IMC, there are 3 channels per IMC,
2 DIMMs per channel.

They support DDR4.

Set DIMM_MAX and DIMM_SPD_SIZE accordingly.

Change-Id: I66cc512465362d5ba04dc36534360c94ca23e77a
Signed-off-by: Jonathan Zhang 
---
M src/soc/intel/xeon_sp/Kconfig
1 file changed, 10 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/43982/1

diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig
index b410dec..cb0a589 100644
--- a/src/soc/intel/xeon_sp/Kconfig
+++ b/src/soc/intel/xeon_sp/Kconfig
@@ -103,4 +103,14 @@
    hex
    default 0x80000

+# 2 IMCs, 3 channel per IMC, 2 DIMMs per channel
+config DIMM_MAX
+	int
+	default 12
+
+# DDR4
+config DIMM_SPD_SIZE
+	int
+	default 512
+
 endif ## SOC_INTEL_XEON_SP