Hello build bot (Jenkins), Furquan Shaikh, Wonkyu Kim, Rizwan Qureshi, Tim Wawrzynczak, Paul Menzel, Alex Levin, Nick Vaccaro, Subrata Banik, Sridhar Siricilla, Kane Chen, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40648
to look at the new patch set (#6).
Change subject: soc/intel/tigerlake: Print HPR_CAUSE0 register and update elog ......................................................................
soc/intel/tigerlake: Print HPR_CAUSE0 register and update elog
In addition to GBLRST_CAUSE0 and GBLRST_CAUSE1, print the value of HPR_CAUSE0. Also call out the CSME-initiated bits from this register and update the elog to include reset causes
Change-Id: Idc57c3cd6a8d156c5544640898e8e7147d34c535 Signed-off-by: derek.huang derek.huang@intel.corp-partner.google.com --- M src/soc/intel/tigerlake/elog.c M src/soc/intel/tigerlake/include/soc/pm.h M src/soc/intel/tigerlake/include/soc/pmc.h M src/soc/intel/tigerlake/pmutil.c 4 files changed, 20 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/40648/6