[coreboot-gerrit] [M] Change in coreboot[master]: mb/intel/mtlrvp: Add romstage and configure DDR5 memory parts

[Harsha B R (Code Review)]

Attention is currently required from: Ashish Kumar Mishra, Wonkyu Kim, Ravishankar Sarawadi, Rizwan Qureshi, Angel Pons, Eric Lai, Tarun Tuli, Jamie Ryu, Tim Wawrzynczak, Harsha B R, Kapil Porwal, Nick Vaccaro, Ronak Kanabar, Raj Astekar, Elyes Haouas.

Harsha B R has uploaded a new patch set (#23) to the change originally created by Jamie Ryu. ( https://review.coreboot.org/c/coreboot/+/66190 )

Change subject: mb/intel/mtlrvp: Add romstage and configure DDR5 memory parts
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mb/intel/mtlrvp: Add romstage and configure DDR5 memory parts

This patch adds initial romstage code and spd data for DDR5 memory
parts for MTL-RVP. This also configures memory based on the board id.

Memory - x32 DDR5 SBS SODIMM 1DPC
Vendor/Model - SK-Hynix/HMCG66MEBSA092N

BUG=b:224325352
TEST=Able to boot intel/mtlrvp (DDR5 SKU) to ChromeOS

Signed-off-by: Jamie Ryu 
Change-Id: I0e1a26d99e170311a89412f44b7cbb0430788f58
Signed-off-by: Harsha B R 
---
M src/mainboard/intel/mtlrvp/Makefile.inc
A src/mainboard/intel/mtlrvp/romstage.c
M src/mainboard/intel/mtlrvp/variants/baseboard/include/baseboard/variants.h
A src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/memory/Makefile.inc
A src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/memory/memory.c
5 files changed, 112 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/66190/23