Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34662 )
Change subject: Documentation/binaries: Add AMD FSP documentation ......................................................................
Patch Set 7:
(16 comments)
https://review.coreboot.org/c/coreboot/+/34662/1/Documentation/binaries/AMD_... File Documentation/binaries/AMD_FSP_family_17h.md:
https://review.coreboot.org/c/coreboot/+/34662/1/Documentation/binaries/AMD_... PS1, Line 19: 1. **No FSP-T** : Because
Will try something on my plugin. If it works, I'll update it and see how it looks in yours. […]
Done
https://review.coreboot.org/c/coreboot/+/34662/1/Documentation/binaries/AMD_... PS1, Line 24: 3. **FSP-M is loaded to DRAM** : PSP can be made to load a section of the flash into RAM before releasing : the reset, thus FSP-M can be made to run directly from memory.
Ok.
Rewritten.
https://review.coreboot.org/c/coreboot/+/34662/1/Documentation/binaries/AMD_... PS1, Line 27: . **FSP-M can be made position independent** : Because it's loaded to memory and does not uses CAR, FSP-M can be made PIC : (Position Independent Code).
Will try.
Done
https://review.coreboot.org/c/coreboot/+/34662/1/Documentation/binaries/AMD_... PS1, Line 32: 1. **Memory fragmentation** : Though FSP still fragments memory, it has added control for flexibility : of where the chunks will reside.
Alex provided this statement, I just rephrase it some.
Asked Alex to change it.
https://review.coreboot.org/c/coreboot/+/34662/1/Documentation/binaries/AMD_... PS1, Line 36: intergers
Again, Alex provided this statement.
Asked Alex to change it.
https://review.coreboot.org/c/coreboot/+/34662/2/Documentation/binaries/amd/... File Documentation/binaries/amd/AMD_FSP_family_17h.md:
https://review.coreboot.org/c/coreboot/+/34662/2/Documentation/binaries/amd/... PS2, Line 12: * Reset vector is not the old 0xFFFFFFF0.
Marshall suggested pointing to family 17h (link), will that suffice?
Done
https://review.coreboot.org/c/coreboot/+/34662/2/Documentation/binaries/amd/... PS2, Line 25: PSP can be made to load a section of the flash into RAM
Will do.
Done
https://review.coreboot.org/c/coreboot/+/34662/6/Documentation/binaries/amd/... File Documentation/binaries/amd/AMD_FSP_family_17h.md:
https://review.coreboot.org/c/coreboot/+/34662/6/Documentation/binaries/amd/... PS6, Line 1: # FSP implementation differences between Intel and AMD
This would be a change from the initial request on issue tracker. […]
Partially done.
https://review.coreboot.org/c/coreboot/+/34662/6/Documentation/binaries/amd/... PS6, Line 17: available.
Yes. Find an editor with a reflow function. […]
Done
https://review.coreboot.org/c/coreboot/+/34662/6/Documentation/binaries/amd/... PS6, Line 21: > Family 17h does not require Cache as RAM and FSP-T calls are unsupported.
It was a way to separate context from bullet point... they were being placed on the same line. […]
Done
https://review.coreboot.org/c/coreboot/+/34662/6/Documentation/binaries/amd/... PS6, Line 25: > obtain the memory map from the PSP.
Yes, as of this instant, FSP-M handles all the AGESA calls and we're not using FSP-S for anything. […]
For patch set 8.
https://review.coreboot.org/c/coreboot/+/34662/6/Documentation/binaries/amd/... PS6, Line 31: uses
will do.
Done
https://review.coreboot.org/c/coreboot/+/34662/6/Documentation/binaries/amd/... PS6, Line 32: a
thanks...
Done
https://review.coreboot.org/c/coreboot/+/34662/6/Documentation/binaries/amd/... PS6, Line 41: intergers
lol typo.
Done
https://review.coreboot.org/c/coreboot/+/34662/6/Documentation/binaries/amd/... PS6, Line 48: make call back
thanks.
Done
https://review.coreboot.org/c/coreboot/+/34662/6/Documentation/binaries/cavi... File Documentation/binaries/cavium/index.md:
PS6:
Ok, as I'm not planning on filling them I shall remove them.
Done