Marc Jones (marc.jones@se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8571
-gerrit
commit 79af2234c8cf6680d33c044afe751dc2e254d521 Author: Furquan Shaikh furquan@google.com Date: Wed Jun 25 11:37:04 2014 -0700
coreboot t132: Remove init pllx for now
We suspect that the code was stuck on init pllx (PLLX - acts as a clock source for the CPU cluster). So removing the init call for pllx. This needs to be added later when required. Also added a few more printks to display the progress.
BUG=None BRANCH=None TEST=Compiles successfully for rush. Print messages seen on serial console.
Original-Change-Id: I70e908a9ce1f3598d68bda68c0401a78834597d1 Original-Signed-off-by: Furquan Shaikh furquan@google.com Original-Reviewed-on: https://chromium-review.googlesource.com/205680 Original-Tested-by: Furquan Shaikh furquan@chromium.org Original-Reviewed-by: Aaron Durbin adurbin@chromium.org Original-Commit-Queue: Furquan Shaikh furquan@chromium.org (cherry picked from commit d557d99edb855fbf7b32231c6746c676041bf62a) Signed-off-by: Marc Jones marc.jones@se-eng.com
Change-Id: Iaf56f2d587708c6e9fb01d4ced2edb5931075a81 --- src/soc/nvidia/tegra132/bootblock.c | 6 +++++- src/soc/nvidia/tegra132/clock.c | 7 ------- 2 files changed, 5 insertions(+), 8 deletions(-)
diff --git a/src/soc/nvidia/tegra132/bootblock.c b/src/soc/nvidia/tegra132/bootblock.c index f377bc1..46b7b3a 100644 --- a/src/soc/nvidia/tegra132/bootblock.c +++ b/src/soc/nvidia/tegra132/bootblock.c @@ -54,12 +54,16 @@ void main(void) if (CONFIG_BOOTBLOCK_CONSOLE) { console_init(); exception_init(); - printk(BIOS_INFO, "Tegra132: Bootblock here\n"); + printk(BIOS_INFO, "T132: Bootblock here\n"); }
clock_init();
+ printk(BIOS_INFO, "T132 bootblock: Clock init done\n"); + bootblock_mainboard_init();
+ printk(BIOS_INFO, "T132 bootblock: Mainboard bootblock init done\n"); + while(1); } diff --git a/src/soc/nvidia/tegra132/clock.c b/src/soc/nvidia/tegra132/clock.c index 9db957c..66eaf1e 100644 --- a/src/soc/nvidia/tegra132/clock.c +++ b/src/soc/nvidia/tegra132/clock.c @@ -519,9 +519,6 @@ void clock_init(void) clrsetbits_le32(&pmc->osc_edpd_over, PMC_OSC_EDPD_OVER_XOFS_MASK, OSC_DRIVE_STRENGTH << PMC_OSC_EDPD_OVER_XOFS_SHIFT);
- /* Disable IDDQ for PLLX before we set it up (from U-Boot -- why?) */ - clrbits_le32(&clk_rst->pllx_misc3, PLLX_IDDQ_MASK); - /* Set up PLLP_OUT(1|2|3|4) divisor to generate (9.6|48|102|204)MHz */ write32((CLK_DIVIDER(TEGRA_PLLP_KHZ, 9600) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT1_SHIFT | @@ -534,10 +531,6 @@ void clock_init(void) PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT4_SHIFT, &clk_rst->pllp_outb);
- /* init pllx */ - init_pll(&clk_rst->pllx_base, &clk_rst->pllx_misc, - osc_table[osc].pllx, PLLPAXS_MISC_LOCK_ENABLE); - /* init pllu */ init_pll(&clk_rst->pllu_base, &clk_rst->pllu_misc, osc_table[osc].pllu, PLLUD_MISC_LOCK_ENABLE);