Michał Kopeć has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63499 )
Change subject: mb/msi/ms7d25: add basic FSP configuration in devicetree ......................................................................
mb/msi/ms7d25: add basic FSP configuration in devicetree
Configure some basic FSP parameters in devicetree for to allow for booting an OS.
Change-Id: Iff227c70d0155ac27d6ffa50a069d154bb7fce3c Signed-off-by: Michał Kopeć michal.kopec@3mdeb.com --- M src/mainboard/msi/ms7d25/devicetree.cb 1 file changed, 69 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/63499/1
diff --git a/src/mainboard/msi/ms7d25/devicetree.cb b/src/mainboard/msi/ms7d25/devicetree.cb index dccaa25..83405ff 100644 --- a/src/mainboard/msi/ms7d25/devicetree.cb +++ b/src/mainboard/msi/ms7d25/devicetree.cb @@ -1,4 +1,73 @@ chip soc/intel/alderlake + # FSP configuration + + # Enable CNVi BT + register "cnvi_bt_core" = "true" + + # Sagv Configuration + register "sagv" = "SaGv_Enabled" + + # USB Configuration + # TODO: Verify + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" + register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" + register "usb2_ports[10]" = "USB2_PORT_MID(OC_SKIP)" + register "usb2_ports[11]" = "USB2_PORT_MID(OC_SKIP)" + register "usb2_ports[12]" = "USB2_PORT_MID(OC_SKIP)" + register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC_SKIP)" + + # LPC generic I/O ranges + register "gen1_dec" = "0x00fc0201" + register "gen2_dec" = "0x003c0a01" + register "gen3_dec" = "0x000c03f1" + register "gen4_dec" = "0x000c0081" + + register "sata_salp_support" = "1" + + register "sata_ports_enable" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + [3] = 1, + [4] = 1, + [5] = 1, + [6] = 1, + [7] = 1, + }" + + register "sata_ports_dev_slp" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + [3] = 1, + [4] = 1, + [5] = 1, + [6] = 1, + [7] = 1, + }" + + # HD Audio + register "pch_hda_dsp_enable" = "1" + device domain 0 on device ref igpu on end device ref crashlog off end @@ -10,17 +79,6 @@ device ref heci3 off end device ref heci4 off end device ref sata on end - device ref pcie_rp1 on end - device ref pcie_rp2 on end - device ref pcie_rp3 on end - device ref pcie_rp4 on end - device ref pcie_rp5 on end - device ref pcie_rp6 on end - device ref pcie_rp7 on end - device ref pcie_rp8 on end - device ref pcie_rp9 on end - device ref pcie_rp10 on end - device ref pcie_rp11 on end device ref p2sb on end device ref hda on end device ref smbus on end