[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Fix overlapping memory address used for early GS...

[Bora Guvendik (Code Review)]

Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47643 )

Change subject: soc/intel/tigerlake: Fix overlapping memory address used for early GSPI2 and UART bars
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Patch Set 1:

Looks like alderlake need the same fix.